From patchwork Tue Apr 16 09:30:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stu Hsieh X-Patchwork-Id: 1086160 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44k0Vj3Cgdz9s00 for ; Tue, 16 Apr 2019 19:31:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728901AbfDPJbN (ORCPT ); Tue, 16 Apr 2019 05:31:13 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:51871 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728989AbfDPJa1 (ORCPT ); Tue, 16 Apr 2019 05:30:27 -0400 X-UUID: 0dd8531c04194150943493b79ebf6dba-20190416 X-UUID: 0dd8531c04194150943493b79ebf6dba-20190416 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 158978725; Tue, 16 Apr 2019 17:30:18 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs03n1.mediatek.inc (172.21.101.181) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 16 Apr 2019 17:30:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 16 Apr 2019 17:30:17 +0800 From: Stu Hsieh To: Mauro Carvalho Chehab , Rob Herring , CK Hu CC: Mark Rutland , Matthias Brugger , Stu Hsieh , , , , , , Subject: [PATCH v2 01/15] dt-bindings: media: Add binding for MT2712 MIPI-CSI2 Date: Tue, 16 Apr 2019 17:30:01 +0800 Message-ID: <1555407015-18130-2-git-send-email-stu.hsieh@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1555407015-18130-1-git-send-email-stu.hsieh@mediatek.com> References: <1555407015-18130-1-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add MIPI-CSI2 dt-binding for Mediatek MT2712 SoC Signed-off-by: Stu Hsieh --- .../bindings/media/mediatek-mipicsi-camsv.txt | 53 ++++++++++++++++++ .../media/mediatek-mipicsi-common.txt | 19 +++++++ .../bindings/media/mediatek-mipicsi.txt | 54 +++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi.txt diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt new file mode 100644 index 000000000000..5f34974f12ac --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt @@ -0,0 +1,53 @@ +* Mediatek MIPI-CSI2 receiver camsv + +Mediatek MIPI-CSI2 receiver camsv transfer data to DRAM in Mediatek SoCs + +Required properties: +- reg : physical base address of the mipicsi receiver registers and length of + memory mapped region. +- clocks: device clocks, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- interrupts : interrupt number to the interrupt controller. + +Example: + seninf1_mux_camsv0: seninf_mux_camsv@15002100 { + reg = <0 0x15002120 0 0x40>, + <0 0x15004000 0 0x1000>; + clocks = <&imgsys CLK_IMG_CAM_SV_EN>; + interrupts = ; + }; + + seninf2_mux_camsv1: seninf_mux_camsv@15002500 { + reg = <0 0x15002520 0 0x40>, + <0 0x15005000 0 0x1000>; + clocks = <&imgsys CLK_IMG_CAM_SV_EN>; + interrupts = ; + }; + + seninf3_mux_camsv2: seninf_mux_camsv@15002900 { + reg = <0 0x15002920 0 0x40>, + <0 0x15006000 0 0x1000>; + clocks = <&imgsys CLK_IMG_CAM_SV1_EN>; + interrupts = ; + }; + + seninf4_mux_camsv3: seninf_mux_camsv@15002D00 { + reg = <0 0x15002D20 0 0x40>, + <0 0x15007000 0 0x1000>; + clocks = <&imgsys CLK_IMG_CAM_SV1_EN>; + interrupts = ; + }; + + seninf5_mux_camsv4: seninf_mux_camsv@15003100 { + reg = <0 0x15003120 0 0x40>, + <0 0x15008000 0 0x1000>; + clocks = <&imgsys CLK_IMG_CAM_SV2_EN>; + interrupts = ; + }; + + seninf6_mux_camsv5: seninf_mux_camsv@15003500 { + reg = <0 0x15003520 0 0x40>, + <0 0x15009000 0 0x1000>; + clocks = <&imgsys CLK_IMG_CAM_SV2_EN>; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt new file mode 100644 index 000000000000..a67c744b75f0 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt @@ -0,0 +1,19 @@ +* Mediatek MIPI-CSI2 receiver common + +Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in Mediatek SoCs + +Required properties: +- compatible: should be "mediatek,mt2712-mipicsi-common" +- reg : physical base address of the mipicsi receiver registers and length of + memory mapped region. +- clocks: device clocks, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. + + +Example: + mipicsi: mipicsi@15002000 { + compatible = "mediatek,mt2712-mipicsi-common", "syscon"; + reg = <0 0x15002000 0 0x10>; + clocks = <&imgsys CLK_IMG_SENINF_CAM_EN>, + <&imgsys CLK_IMG_SENINF_SCAM_EN>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt new file mode 100644 index 000000000000..24741ed62b25 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt @@ -0,0 +1,54 @@ +* Mediatek MIPI-CSI2 receiver + +Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in Mediatek SoCs + +Required properties: +- compatible: should be "mediatek,mt2712-mipicsi" +- reg : physical base address of the mipicsi receiver registers and length of + memory mapped region. +- power-domains: a phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details. +- mediatek,larb: must contain the local arbiters in the current Socs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details. +- iommus: should point to the respective IOMMU block with master port as + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt + for details. +- mediatek,seninf_mux_camsv: seninf_mux_camsv the data go through of the mipicsi port +- mediatek,mipicsiid: the id of the mipicsi port +- mediatek,mipicsi: the common component of the two mipicsi port + +Example: + mipicsi0: mipicsi@10217000 { + compatible = "mediatek,mt2712-mipicsi"; + mediatek,mipicsi = <&mipicsi>; + iommus = <&iommu0 M4U_PORT_CAM_DMA0>, + <&iommu0 M4U_PORT_CAM_DMA1>; + mediatek,larb = <&larb2>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; + + mediatek,seninf_mux_camsv = <&seninf1_mux_camsv0 + &seninf2_mux_camsv1 + &seninf3_mux_camsv2 + &seninf4_mux_camsv3>; + reg = <0 0x10217000 0 0x60>, + <0 0x15002100 0 0x4>, + <0 0x15002300 0 0x100>; + mediatek,mipicsiid = <0>; + status="disabled"; + }; + + mipicsi1: mipicsi@10218000 { + compatible = "mediatek,mt2712-mipicsi"; + mediatek,mipicsi = <&mipicsi>; + iommus = <&iommu0 M4U_PORT_CAM_DMA2>; + mediatek,larb = <&larb2>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; + mediatek,seninf_mux_camsv = <&seninf5_mux_camsv4 + &seninf6_mux_camsv5>; + reg = <0 0x10218000 0 0x60>, + <0 0x15002500 0 0x4>, + <0 0x15002700 0 0x100>; + mediatek,mipicsiid = <1>; + status="disabled"; + }; \ No newline at end of file