From patchwork Mon Apr 15 10:10:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Gorski X-Patchwork-Id: 1085555 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Znubu+SB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44jPQl44V8z9s47 for ; Mon, 15 Apr 2019 20:10:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726313AbfDOKKz (ORCPT ); Mon, 15 Apr 2019 06:10:55 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:36277 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725885AbfDOKKz (ORCPT ); Mon, 15 Apr 2019 06:10:55 -0400 Received: by mail-wm1-f68.google.com with SMTP id h18so19630746wml.1; Mon, 15 Apr 2019 03:10:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cSD6PBow7v0W8TwFUmI5O2Pxk6CBw7ocNAAJAAXdWg8=; b=Znubu+SBnrloeNAT8sZMfuxqeFCVL60+47/i85ZzPS2cuhM8KEu6rEJmwddEvfM/hN 8OMOgxgRo3C+7g+dQ9yMUA7FD3kUFXHByFUZmOD1FfqUpnaQYevYG6u+3orpJtLY7MDi fXKlHkpbpnv57up630V0jzQwAEm+nNyB+6hKhhhYfGlZ28qMJitYKjLQDvBIMXjs13VA sSuRsFrhSiVlJlmJIxdqNl9kOo0nwazv/ZkUTF3o/jkzKn9qJZItZMEGF41KR9bfzSYD SfSYhh6daMKDFH3gI22x6lXl8KGapgnYmxc0N9yrtXYfkZczK37KlYK0gSEqilvOYkwL 5tsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cSD6PBow7v0W8TwFUmI5O2Pxk6CBw7ocNAAJAAXdWg8=; b=YjH4Q3vv4uQquYWxbEx3AzCd1xQeDzihD4dMTd2udg3s9W/i2FKAxFrq0j/8NePRXP 3hOLgqPrVtv5H+MiFL5VhPnkrwGskpD9kxtl2SwbKILkSAeiGsonFHBdOSRdULDsq5bV GEQeiym33Ox4iveRwVlixVRyI7kUflCPc8WTPTq4qw5elF0SROhUnftx1i7/rAmE3BDU nOKg89o9dGS9wWYQP+mUtKYLgDyf84NoRlC/7dfqszdQYTK/9bxFQEYc0JBxYsRjrNzu 8bMknoDTVDT8q3rHso9WYcHhIYtQrZJYtI+SDKQEY5Rez6gXoglldglDWmr2sA19FqVj WdUg== X-Gm-Message-State: APjAAAXVXGAab7MtrfechqsEKHmYO/rdJZt1PSZ3N/SZvxw3VoOFP2d1 YW7LjGJKEmTvnxWjZUHgmx2urkmWn7Q= X-Google-Smtp-Source: APXvYqzNxdl1PhIO1oOobESMBfrW0DrNzXt6hIBogeVrQpk/WjkC/3DOHfN+kDsMgbMux6PsbVAqxA== X-Received: by 2002:a7b:cd95:: with SMTP id y21mr21860173wmj.29.1555323052152; Mon, 15 Apr 2019 03:10:52 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id d6sm11592214wrp.9.2019.04.15.03.10.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 03:10:51 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Cc: Anatolij Gustschin , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Stuebner , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Michal Simek Subject: [PATCH RFT V2 1/8] clk: divider: add explicit big endian support Date: Mon, 15 Apr 2019 12:10:39 +0200 Message-Id: <20190415101046.5872-2-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190415101046.5872-1-jonas.gorski@gmail.com> References: <20190415101046.5872-1-jonas.gorski@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add a clock specific flag to switch register accesses to big endian, to allow runtime configuration of big endian divider clocks. Signed-off-by: Jonas Gorski --- V1 -> V2: * switch from global to local flag drivers/clk/clk-divider.c | 26 ++++++++++++++++++++++---- include/linux/clk-provider.h | 4 ++++ 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index e5a17265cfaf..ff791a7a5e9e 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -25,6 +25,24 @@ * parent - fixed parent. No clk_set_parent support */ +static inline u32 clk_div_readl(struct clk_divider *divider) +{ + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + return ioread32be(divider->reg); + else + return clk_readl(divider->reg); +} + +static inline void clk_div_writel(struct clk_divider *divider, u32 val) +{ + if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) + iowrite32be(val, divider->reg); + else + clk_writel(val, divider->reg); +} + +#define div_mask(width) ((1 << (width)) - 1) + static unsigned int _get_table_maxdiv(const struct clk_div_table *table, u8 width) { @@ -135,7 +153,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, struct clk_divider *divider = to_clk_divider(hw); unsigned int val; - val = clk_readl(divider->reg) >> divider->shift; + val = clk_div_readl(divider) >> divider->shift; val &= clk_div_mask(divider->width); return divider_recalc_rate(hw, parent_rate, val, divider->table, @@ -370,7 +388,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_READ_ONLY) { u32 val; - val = clk_readl(divider->reg) >> divider->shift; + val = clk_div_readl(divider->reg) >> divider->shift; val &= clk_div_mask(divider->width); return divider_ro_round_rate(hw, rate, prate, divider->table, @@ -420,11 +438,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { val = clk_div_mask(divider->width) << (divider->shift + 16); } else { - val = clk_readl(divider->reg); + val = clk_div_readl(divider->reg); val &= ~(clk_div_mask(divider->width) << divider->shift); } val |= (u32)value << divider->shift; - clk_writel(val, divider->reg); + clk_div_writel(divider, val); if (divider->lock) spin_unlock_irqrestore(divider->lock, flags); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index db21437c77e2..7117b8cc0c0c 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -416,6 +416,9 @@ struct clk_div_table { * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED * except when the value read from the register is zero, the divisor is * 2^width of the field. + * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used + * for the divider register. Setting this flag makes the register accesses + * big endian. */ struct clk_divider { struct clk_hw hw; @@ -437,6 +440,7 @@ struct clk_divider { #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +#define CLK_DIVIDER_BIG_ENDIAN BIT(7) extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; From patchwork Mon Apr 15 10:10:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Gorski X-Patchwork-Id: 1085556 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gztGjS1h"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44jPQm5fn6z9s5c for ; Mon, 15 Apr 2019 20:10:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725885AbfDOKK4 (ORCPT ); Mon, 15 Apr 2019 06:10:56 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:35505 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726287AbfDOKK4 (ORCPT ); Mon, 15 Apr 2019 06:10:56 -0400 Received: by mail-wr1-f65.google.com with SMTP id w1so21151660wrp.2; Mon, 15 Apr 2019 03:10:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=o+W2Q634iC3zR2xiEnI5jQwiq7sivbZ81nwPB9eB+tU=; b=gztGjS1hRk4mVTO/iq0Zf3l+AJuYNqz3qjgBMCKMLcEtjTKD1dvxU280eEopc1zqjp 3mVduNg2l6/zUug56BWIGoXgTufkNUR1/GVyyxNeN/v0wFu5hSzGt9z0pBZrFdjHT2JJ FEJBOb31onNhjnwqgxnUDN+Ht3ExstBL4lIlKhhOsIzbsvbedk2DPwC7LDCjnx0hnf3J 6fGKL1Vy9WALTgeQXrtDvb3HvSuH453GwBjxEeLvHiwKJ1KWfowHFSpApbN/60681UAx S7F5tovZ3qcr/9qOTlt2gVrRqjl1AErzJq1UEmFkoH2+C4RrlnByh7gdGymRaUO1IKuX 6YLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=o+W2Q634iC3zR2xiEnI5jQwiq7sivbZ81nwPB9eB+tU=; b=sH85ZVgqLb3EWc4ouHEjJG8V6/O0urerzJHGaqD0cG+gBksKOpn1CPO8RBP8GYK8x0 qx6XwNqxN/pu0cefuCJFBsS8H2O3DmJ5wQZzDbaqxa0Hf0Yh2P2gOjX2Mau2TtHZYjXg Up10CcQWf1cAF5+/6ZgQ0h3IxczoxTXK5LlG/zVuZYsTvbZs9y9aYInPI/vucT6Dk9bj /PrEPo7QQQrAsmRIaQmq33rpAXc0M9frxVBHBvBoh9ZDKm+bk5r13593qLiBjWFkwCRk H2Yv1bT2Mz9d7Rf8m5pVq4oC4/YSaoXoyhl17ja9Dvy9o2t1Co/eOL0SNufbvZ4+CbRU V40g== X-Gm-Message-State: APjAAAUQrhfWPRitY7He8pLg1spxCZHzTVkmPUdmySyDocs2gvhA1cB+ ZbHb6YF4A3s7G62iIUJDEz4RRX5sr9E= X-Google-Smtp-Source: APXvYqwjGrmwlbP67cAxOBoWrpPk6FwlPj8xUIyK9GJsk2OjFotgQsFgHX7W7vJb9Un2uuMuRW2EUg== X-Received: by 2002:a05:6000:1286:: with SMTP id f6mr13099948wrx.93.1555323053789; Mon, 15 Apr 2019 03:10:53 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id d6sm11592214wrp.9.2019.04.15.03.10.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 03:10:53 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Cc: Anatolij Gustschin , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Stuebner , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Michal Simek Subject: [PATCH RFT V2 2/8] clk: fractional-divider: add explicit big endian support Date: Mon, 15 Apr 2019 12:10:40 +0200 Message-Id: <20190415101046.5872-3-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190415101046.5872-1-jonas.gorski@gmail.com> References: <20190415101046.5872-1-jonas.gorski@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add a clock specific flag to switch register accesses to big endian, to allow runtime configuration of big endian fractional divider clocks. Signed-off-by: Jonas Gorski --- V1 -> V2: * newly added patch drivers/clk/clk-fractional-divider.c | 22 +++++++++++++++++++--- include/linux/clk-provider.h | 4 ++++ 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index fdfe2e423d15..b9988d3b3828 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -13,6 +13,22 @@ #include #include +static inline u32 clk_fd_readl(struct clk_fractional_divider *fd) +{ + if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN) + return ioread32be(fd->reg); + else + return clk_readl(fd->reg); +} + +static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val) +{ + if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN) + iowrite32be(val, fd->reg); + else + clk_writel(val, fd->reg); +} + static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -27,7 +43,7 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, else __acquire(fd->lock); - val = clk_readl(fd->reg); + val = clk_fd_readl(fd); if (fd->lock) spin_unlock_irqrestore(fd->lock, flags); @@ -115,10 +131,10 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, else __acquire(fd->lock); - val = clk_readl(fd->reg); + val = clk_fd_readl(fd); val &= ~(fd->mmask | fd->nmask); val |= (m << fd->mshift) | (n << fd->nshift); - clk_writel(val, fd->reg); + clk_fd_writel(fd, val); if (fd->lock) spin_unlock_irqrestore(fd->lock, flags); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 7117b8cc0c0c..8c07d810acf5 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -607,6 +607,9 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED * is set then the numerator and denominator are both the value read * plus one. + * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are + * used for the divider register. Setting this flag makes the register + * accesses big endian. */ struct clk_fractional_divider { struct clk_hw hw; @@ -627,6 +630,7 @@ struct clk_fractional_divider { #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) +#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, From patchwork Mon Apr 15 10:10:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Gorski X-Patchwork-Id: 1085557 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rvd99lJG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44jPQq1XVWz9s71 for ; Mon, 15 Apr 2019 20:10:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726095AbfDOKK6 (ORCPT ); Mon, 15 Apr 2019 06:10:58 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:51636 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726287AbfDOKK6 (ORCPT ); Mon, 15 Apr 2019 06:10:58 -0400 Received: by mail-wm1-f67.google.com with SMTP id 4so19880857wmf.1; Mon, 15 Apr 2019 03:10:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0DzTJysZxO15MPQ7kqYMW+n479fJgtxXcOuK6TSaMOY=; b=rvd99lJGUbu0PxIfKZBydyMyHcMRBVRstZMvv7xY86ibl0HhEWK6WLbj4kToX2g5c+ kpvz8UEBYyKpYwK/LmVh6c7orT1KPp5CmN+qZahxMfllHlE86MOyWEN8ekUc1XGt3Rgt KugqFdGcBiGk24zQ+g4PNL1pGUi14PiLUbHjI/87Ht0TpCldR9JAYf3xKTVRfdJRfPE+ JgVdX89pzQovf2vyHTytIrczXYVYx1PrgGSnn85RtYZkSIF/BfMt52XT28AM5ucwadWW svWpsLin2Fq3UfQIMeA8dLmFF69fFfEetIc3SFWXFJWlSeqsKo/IKEZtXW6ZXdH/0BzI f/GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0DzTJysZxO15MPQ7kqYMW+n479fJgtxXcOuK6TSaMOY=; b=QeMHUuJZYM1EP1mRJKAmRHOSvcNeQaw24P6Gd8rnG1Z9KkQUVLv0W3phC+QoPq9ZVd dmPvYFSNztNii8voh6iRZewHxtNPOZ1kvTqbyQhw+0qSKkRcBOs+ht6inEstPnyMQ6Z3 kvBt7od6TUNmC+8uJOyzTs5rJNr2wk+YhxJ9KlvDw8pJTXcAxfuzvprjrh+l3XKDO2Aj mMGvOGWWGA/YPXkknMGD3jc7ReThcUdTfKzE2suzmQ1BdIDDf38ORJWFIYdojmtvQe+E xRWqEI+Ncy5WHAQhvpULpasanXrb89qxQYbNmQ6sadXidBA7O6PkGdBDjdy3Wkh6AsaZ yEfw== X-Gm-Message-State: APjAAAXZU1EHIIpnV/IcJO8SVqqmBicqfj7neqCRV3ltoKqj263PB7NC eweWLUN9m3s+u4J4XBuhqIAN9ZxsqxQ= X-Google-Smtp-Source: APXvYqxsvH0Rc7MHGSQ5oXiwFD2EUfMonfSwzm6bqTZnIhCPTVMeStUOT1R7Tz14Ms6g+WEJB2kWAw== X-Received: by 2002:a05:600c:24f:: with SMTP id 15mr22249991wmj.48.1555323056233; Mon, 15 Apr 2019 03:10:56 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id d6sm11592214wrp.9.2019.04.15.03.10.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 03:10:55 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Cc: Anatolij Gustschin , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Stuebner , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Michal Simek Subject: [PATCH RFT V2 3/8] clk: gate: add explicit big endian support Date: Mon, 15 Apr 2019 12:10:41 +0200 Message-Id: <20190415101046.5872-4-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190415101046.5872-1-jonas.gorski@gmail.com> References: <20190415101046.5872-1-jonas.gorski@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add a clock specific flag to switch register accesses to big endian, to allow runtime configuration of big endian gated clocks. Signed-off-by: Jonas Gorski --- V1 -> V2: * switch from global to local flag drivers/clk/clk-gate.c | 22 +++++++++++++++++++--- include/linux/clk-provider.h | 4 ++++ 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index f05823cd9b21..521e112ef5b5 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -23,6 +23,22 @@ * parent - fixed parent. No clk_set_parent support */ +static inline u32 clk_gate_readl(struct clk_gate *gate) +{ + if (gate->flags & CLK_GATE_BIG_ENDIAN) + return ioread32be(gate->reg); + else + return clk_readl(gate->reg); +} + +static inline void clk_gate_writel(struct clk_gate *gate, u32 val) +{ + if (gate->flags & CLK_GATE_BIG_ENDIAN) + iowrite32be(val, gate->reg); + else + clk_writel(val, gate->reg); +} + /* * It works on following logic: * @@ -55,7 +71,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) if (set) reg |= BIT(gate->bit_idx); } else { - reg = clk_readl(gate->reg); + reg = clk_gate_readl(gate); if (set) reg |= BIT(gate->bit_idx); @@ -63,7 +79,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) reg &= ~BIT(gate->bit_idx); } - clk_writel(reg, gate->reg); + clk_gate_writel(gate, reg); if (gate->lock) spin_unlock_irqrestore(gate->lock, flags); @@ -88,7 +104,7 @@ int clk_gate_is_enabled(struct clk_hw *hw) u32 reg; struct clk_gate *gate = to_clk_gate(hw); - reg = clk_readl(gate->reg); + reg = clk_gate_readl(gate); /* if a set bit disables this clk, flip it before masking */ if (gate->flags & CLK_GATE_SET_TO_DISABLE) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 8c07d810acf5..8576c2dbc639 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -348,6 +348,9 @@ void of_fixed_clk_setup(struct device_node *np); * of this register, and mask of gate bits are in higher 16-bit of this * register. While setting the gate bits, higher 16-bit should also be * updated to indicate changing gate bits. + * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for + * the gate register. Setting this flag makes the register accesses big + * endian. */ struct clk_gate { struct clk_hw hw; @@ -361,6 +364,7 @@ struct clk_gate { #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) +#define CLK_GATE_BIG_ENDIAN BIT(2) extern const struct clk_ops clk_gate_ops; struct clk *clk_register_gate(struct device *dev, const char *name, From patchwork Mon Apr 15 10:10:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Gorski X-Patchwork-Id: 1085559 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="unVegUez"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44jPQr4zCqz9s9T for ; Mon, 15 Apr 2019 20:11:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726891AbfDOKLA (ORCPT ); Mon, 15 Apr 2019 06:11:00 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:40436 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726287AbfDOKLA (ORCPT ); Mon, 15 Apr 2019 06:11:00 -0400 Received: by mail-wm1-f66.google.com with SMTP id z24so19740462wmi.5; Mon, 15 Apr 2019 03:10:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OdocwXwJ3rh4kwfXC02eb0oWwurnzLR9MAj+DB02QVg=; b=unVegUezf3xp5NAJ3uaaFz2qj1jvI7tB9oNDrgZUIg3ywpAxWLOr1z8t3mHOXUqUB3 ni6AtLJTn3FK/ozoiLTJSQ0MTx9xY3NgwZb4LpZ+HssMdoKX/IUzPcyg++RFKz02069V JV6IVqMrSGl87D3L0dW4Bx832kjL7/RJGvEqNDxO+Zsi41aFBdzqEe8kTw2ZNaBhv0X3 RCD9UMLh/II2owi+ncMQFtPW9465GQVwF7DNgNK+3gKo+ygzx57N/+7SpXCvR3wvT/m6 nCGNPIEp39TdRYKfA3nPvCRuIds7NI7VBDu3Ae/yXYsgJQnrBAPCMqqJos+eHoYKA9Ui EpkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OdocwXwJ3rh4kwfXC02eb0oWwurnzLR9MAj+DB02QVg=; b=pNp+v6Pk7+UAL2bmS0/K26xRQozHch7FcFq1Pio/yLoj+DoX9+RKkfSnmEonnjLqtW ErkBjpWvtjYcLd80g2lksqm7UzcHHyCjLgWvrZK8Y5E91XN3b90RVOhyeiVu3CJl7zC8 tggAQhQodwzn31R3z2JXsQSDprmIFqIOLJgV5otV+9cRvY20rCBwhnXXhkn0xDuURFbK +x9kNvFomPX1Ls9V1cK4jOr1SdWUffZq2QZsbJyIgWerN/jTJSL+mJEu9L8c1w18irSQ RJuyvAGICDHkBX0nTe3mHo5BdTk+rLQMdUsmGUpPEKXwmdnxoT7Bxz3+ufffzXOl+6m9 ViQQ== X-Gm-Message-State: APjAAAUEaiDAad1J8HBYbAV0Tyv/kcdBMAPZ9cqF/9z+ieAH2kLfPKfF YJiLaFwkSZa5wVnXwFqMRyU8khX+KeE= X-Google-Smtp-Source: APXvYqxQ8qfQOyCV+Mgmqtj6HKEKkrAY4bniNY5tMWURoN0nFwuxCZuqpTFJI+y9FSrpJlXQV9gxpw== X-Received: by 2002:a7b:cf2b:: with SMTP id m11mr19829090wmg.56.1555323058192; Mon, 15 Apr 2019 03:10:58 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id d6sm11592214wrp.9.2019.04.15.03.10.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 03:10:57 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Cc: Anatolij Gustschin , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Stuebner , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Michal Simek Subject: [PATCH RFT V2 4/8] clk: multiplier: add explicit big endian support Date: Mon, 15 Apr 2019 12:10:42 +0200 Message-Id: <20190415101046.5872-5-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190415101046.5872-1-jonas.gorski@gmail.com> References: <20190415101046.5872-1-jonas.gorski@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add a clock specific flag to switch register accesses to big endian, to allow runtime configuration of big endian multiplier clocks. Signed-off-by: Jonas Gorski --- V1 -> V2: * newly added patch drivers/clk/clk-multiplier.c | 22 +++++++++++++++++++--- include/linux/clk-provider.h | 4 ++++ 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-multiplier.c b/drivers/clk/clk-multiplier.c index 3c86f859c199..fb032f7dd407 100644 --- a/drivers/clk/clk-multiplier.c +++ b/drivers/clk/clk-multiplier.c @@ -11,6 +11,22 @@ #include #include +static inline u32 clk_mult_readl(struct clk_multiplier *mult) +{ + if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) + return ioread32be(mult->reg); + else + return clk_readl(mult->reg); +} + +static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val) +{ + if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) + iowrite32be(val, mult->reg); + else + clk_writel(val, mult->reg); +} + static unsigned long __get_mult(struct clk_multiplier *mult, unsigned long rate, unsigned long parent_rate) @@ -27,7 +43,7 @@ static unsigned long clk_multiplier_recalc_rate(struct clk_hw *hw, struct clk_multiplier *mult = to_clk_multiplier(hw); unsigned long val; - val = clk_readl(mult->reg) >> mult->shift; + val = clk_mult_readl(mult) >> mult->shift; val &= GENMASK(mult->width - 1, 0); if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS) @@ -118,10 +134,10 @@ static int clk_multiplier_set_rate(struct clk_hw *hw, unsigned long rate, else __acquire(mult->lock); - val = clk_readl(mult->reg); + val = clk_mult_readl(mult); val &= ~GENMASK(mult->width + mult->shift - 1, mult->shift); val |= factor << mult->shift; - clk_writel(val, mult->reg); + clk_mult_writel(mult, val); if (mult->lock) spin_unlock_irqrestore(mult->lock, flags); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 8576c2dbc639..9df78e3fb62b 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -667,6 +667,9 @@ void clk_hw_unregister_fractional_divider(struct clk_hw *hw); * leaving the parent rate unmodified. * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be * rounded to the closest integer instead of the down one. + * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are + * used for the multiplier register. Setting this flag makes the register + * accesses big endian. */ struct clk_multiplier { struct clk_hw hw; @@ -681,6 +684,7 @@ struct clk_multiplier { #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) +#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) extern const struct clk_ops clk_multiplier_ops; From patchwork Mon Apr 15 10:10:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Gorski X-Patchwork-Id: 1085560 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XlQeaea1"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44jPQv1cbKz9s5c for ; Mon, 15 Apr 2019 20:11:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726046AbfDOKLC (ORCPT ); Mon, 15 Apr 2019 06:11:02 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:36297 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726287AbfDOKLC (ORCPT ); Mon, 15 Apr 2019 06:11:02 -0400 Received: by mail-wm1-f66.google.com with SMTP id h18so19631417wml.1; Mon, 15 Apr 2019 03:11:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GrboAZF3BnjJNJvt9JLXUkPnL7d9/yHPsH0HVH2JN4Y=; b=XlQeaea1fDY3FHmAXvyH27UaBMFNPOXHyoCRGBshG0SHeWTFfslSQE8WAxpWcXgJs2 PdsSiorJe2WTrLDAC69mefgxeAhBOyglj5gR6wLQzENFv9gmWxQQeATXdlSIUYtgwHcS x00R0q6jtOop5hQ2AAFufqZLDQf9MOgYgC7CHL2+8C/zNPBeJVH84mL87+CwDct0AQWT PJzp5Vcv4IT0nIg+XvNP5hSzSjkQb/D/yViyBn/rLi5uC5tNUZ1CHIsHc94+LQeiNrBF 5v7MBqUvQE1AJkvV1E2NWjGn6HxKgMvAJkPSR2G7ydyUeBEooyvfoMDwuYT1jFeUqw2h 4kqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GrboAZF3BnjJNJvt9JLXUkPnL7d9/yHPsH0HVH2JN4Y=; b=gpA67QoNpt4xszVW8F4Ks0jQEk4UfjDWbTuuGPMiw2eoSqBIj33hh8b3PI/ZpeKnaq tkhesV0lLvfr8qLLhigpS0maa7dn+8KsNlITSIEaU63y0jqXLFgWWnTyoM6sjehD5qwl Tzzi3syBZ/60bytqagRr4/nzhuWM9demOhaP1HVP0OpXJi+pkcyhfxHoZ9Lcsfwb81Bo Jywu07400s3V8AWrdExT9jzBZX5xOuNARN/l3jpGyP1rURBTB4AfFF9L3voXIBmlE43R kFBctE+r+QbolRH86SzpqrKlTjGf4HlcAV+vPeTSOX6tbfCW7Fj8IZLJMw7dE1Gsk41N 9cxw== X-Gm-Message-State: APjAAAWUcWVHkncJtLbKwl5u7/YkbbqhPph8npC6Zbg/L/UHEdFBihfS qIhgzRMjzQaES3icWv9znAzAaDH0C8A= X-Google-Smtp-Source: APXvYqx4YIrnaKjtFxaqoF6x/Hk55DKfuyQGcZX+zQoPcFihiNiCA3oA8O89/p25+iSx3jZReIhnvA== X-Received: by 2002:a1c:4187:: with SMTP id o129mr21175746wma.57.1555323060365; Mon, 15 Apr 2019 03:11:00 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id d6sm11592214wrp.9.2019.04.15.03.10.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 03:10:59 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Cc: Anatolij Gustschin , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Stuebner , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Michal Simek Subject: [PATCH RFT V2 5/8] clk: mux: add explicit big endian support Date: Mon, 15 Apr 2019 12:10:43 +0200 Message-Id: <20190415101046.5872-6-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190415101046.5872-1-jonas.gorski@gmail.com> References: <20190415101046.5872-1-jonas.gorski@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add a clock specific flag to switch register accesses to big endian, to allow runtime configuration of big endian mux clocks. Signed-off-by: Jonas Gorski --- V1 -> V2: * switch from global to local flag drivers/clk/clk-mux.c | 22 +++++++++++++++++++--- include/linux/clk-provider.h | 4 ++++ 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 2ad2df2e8909..47f6f4f55f08 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -23,6 +23,22 @@ * parent - parent is adjustable through clk_set_parent */ +static inline u32 clk_mux_readl(struct clk_mux *mux) +{ + if (mux->flags & CLK_MUX_BIG_ENDIAN) + return ioread32be(mux->reg); + else + return clk_readl(mux->reg); +} + +static inline void clk_mux_writel(struct clk_mux *mux, u32 val) +{ + if (mux->flags & CLK_MUX_BIG_ENDIAN) + iowrite32be(val, mux->reg); + else + clk_writel(val, mux->reg); +} + int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, unsigned int val) { @@ -73,7 +89,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) struct clk_mux *mux = to_clk_mux(hw); u32 val; - val = clk_readl(mux->reg) >> mux->shift; + val = clk_mux_readl(mux) >> mux->shift; val &= mux->mask; return clk_mux_val_to_index(hw, mux->table, mux->flags, val); @@ -94,12 +110,12 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) if (mux->flags & CLK_MUX_HIWORD_MASK) { reg = mux->mask << (mux->shift + 16); } else { - reg = clk_readl(mux->reg); + reg = clk_mux_readl(mux); reg &= ~(mux->mask << mux->shift); } val = val << mux->shift; reg |= val; - clk_writel(reg, mux->reg); + clk_mux_writel(mux, reg); if (mux->lock) spin_unlock_irqrestore(mux->lock, flags); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 9df78e3fb62b..f82cda41e1a8 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -510,6 +510,9 @@ void clk_hw_unregister_divider(struct clk_hw *hw); * .get_parent clk_op. * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired * frequency. + * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for + * the mux register. Setting this flag makes the register accesses big + * endian. */ struct clk_mux { struct clk_hw hw; @@ -528,6 +531,7 @@ struct clk_mux { #define CLK_MUX_HIWORD_MASK BIT(2) #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ #define CLK_MUX_ROUND_CLOSEST BIT(4) +#define CLK_MUX_BIG_ENDIAN BIT(5) extern const struct clk_ops clk_mux_ops; extern const struct clk_ops clk_mux_ro_ops; From patchwork Mon Apr 15 10:10:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Gorski X-Patchwork-Id: 1085561 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Qi8BP0Az"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44jPQw4tlfz9s71 for ; Mon, 15 Apr 2019 20:11:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727028AbfDOKLE (ORCPT ); Mon, 15 Apr 2019 06:11:04 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:39009 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726287AbfDOKLE (ORCPT ); Mon, 15 Apr 2019 06:11:04 -0400 Received: by mail-wr1-f65.google.com with SMTP id j9so21126594wrn.6; Mon, 15 Apr 2019 03:11:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1utUG9oo11jNXQpQkS4fRJ6SG9XxN3l3dVfTXDmhkww=; b=Qi8BP0AzvIj0CLEGzLnz/Oj66x7Dup5/AB4St3neDWs+l/i0yiEZGoj2S4lnmAo91j 6/Qv4T6XF36DDGNKBw+wk0oFjNaEZQipRQAFa25p/OHpCu/QtsYR1hcziqSoKRGMFM9K LCDXH/dTI5b0GTYpzcbOvk4ZRiG/pKpdi7ZvbIEGE5ISd8pPn04AmqjSYmOwOHhQ/pyo iSrtKlnKUuDzZUg6NFMOpDFbl737JjXPmWD/NW671VrdazNDzygD6zM8hh+3A1v2/wy8 MYN6yFc7198iiPRhhsd3HyhW8VLm+sFt6x6mgoeq7p7W2zSzm99BSUO+VEsNocKqwZ/m 08Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1utUG9oo11jNXQpQkS4fRJ6SG9XxN3l3dVfTXDmhkww=; b=oUKT7o5F7Yxv79dxGD892HSpbfysk7DTcVl9ejE05+Vb4eLmK1DEtQbdEMethtu3wn 1Gp27a5iK6y2iZsOLuR13JRh3S/1HtBgMCMAzyvPbkcvwCGdGxZ1BVw62IB9rNdssQZC TmvMz+fNhZhZRjLpvDcXuav8nOY1KbN28cKR0mNKiZChbb9cc+DNM2nSXUjnydfaQP0l Wuy0p4zXHQ1QFZ5X+qmEF8SEAhnEvSNzQ3/0hh2x5E0mIMncGo6sWZvuIuikmvH6sHjc 4WG0wLIxM5dRe8qQQdE45T0FIosryJGZkgc1Tv70ALN5I9OgLL3FwRaGj87hy8BlojiU NsqQ== X-Gm-Message-State: APjAAAUfqjft0x5arolDGNfsYoAX5/vCixIO1CIC6HKIazaU8LsiCm0j vht1tAEVCi9MuQtYSZyROhWW6ZyZaDc= X-Google-Smtp-Source: APXvYqzDXCPaXtO/0J6yWiR1mbQTpGNquiOsxi0UOZGLzVVoYvpAf+tZqDLVoX6afIm4E1NjyaPrJQ== X-Received: by 2002:a5d:6646:: with SMTP id f6mr25387wrw.68.1555323062247; Mon, 15 Apr 2019 03:11:02 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id d6sm11592214wrp.9.2019.04.15.03.11.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 03:11:01 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Cc: Anatolij Gustschin , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Stuebner , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Michal Simek Subject: [PATCH RFT V2 6/8] powerpc/512x: mark clocks as big endian Date: Mon, 15 Apr 2019 12:10:44 +0200 Message-Id: <20190415101046.5872-7-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190415101046.5872-1-jonas.gorski@gmail.com> References: <20190415101046.5872-1-jonas.gorski@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org These clocks' registers are accessed as big endian, so mark them as such. Signed-off-by: Jonas Gorski --- V1 -> V2: * switch from global to local flags arch/powerpc/platforms/512x/clock-commonclk.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c index b3097fe6441b..0072330350fa 100644 --- a/arch/powerpc/platforms/512x/clock-commonclk.c +++ b/arch/powerpc/platforms/512x/clock-commonclk.c @@ -240,7 +240,8 @@ static inline struct clk *mpc512x_clk_divider( u32 __iomem *reg, u8 pos, u8 len, int divflags) { return clk_register_divider(NULL, name, parent_name, clkflags, - reg, pos, len, divflags, &clklock); + reg, pos, len, + divflags | CLK_DIVIDER_BIG_ENDIAN, &clklock); } static inline struct clk *mpc512x_clk_divtable( @@ -250,7 +251,7 @@ static inline struct clk *mpc512x_clk_divtable( { u8 divflags; - divflags = 0; + divflags = CLK_DIVIDER_BIG_ENDIAN; return clk_register_divider_table(NULL, name, parent_name, 0, reg, pos, len, divflags, divtab, &clklock); @@ -261,10 +262,12 @@ static inline struct clk *mpc512x_clk_gated( u32 __iomem *reg, u8 pos) { int clkflags; + u8 gateflags; clkflags = CLK_SET_RATE_PARENT; + gateflags = CLK_GATE_BIG_ENDIAN; return clk_register_gate(NULL, name, parent_name, clkflags, - reg, pos, 0, &clklock); + reg, pos, gateflags, &clklock); } static inline struct clk *mpc512x_clk_muxed(const char *name, @@ -275,7 +278,7 @@ static inline struct clk *mpc512x_clk_muxed(const char *name, u8 muxflags; clkflags = CLK_SET_RATE_PARENT; - muxflags = 0; + muxflags = CLK_MUX_BIG_ENDIAN; return clk_register_mux(NULL, name, parent_names, parent_count, clkflags, reg, pos, len, muxflags, &clklock); From patchwork Mon Apr 15 10:10:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Gorski X-Patchwork-Id: 1085562 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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Mon, 15 Apr 2019 03:11:04 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id d6sm11592214wrp.9.2019.04.15.03.11.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 03:11:03 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Cc: Anatolij Gustschin , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Stuebner , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Michal Simek Subject: [PATCH RFT V2 7/8] clk: core: remove powerpc special handling Date: Mon, 15 Apr 2019 12:10:45 +0200 Message-Id: <20190415101046.5872-8-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190415101046.5872-1-jonas.gorski@gmail.com> References: <20190415101046.5872-1-jonas.gorski@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that the powerpc clocks are properly marked as big endian, we can remove the special handling for PowerPC. Signed-off-by: Jonas Gorski --- V1 -> V2: * no actual changes include/linux/clk-provider.h | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index f82cda41e1a8..479e616ce7f5 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1001,20 +1001,6 @@ static inline int of_clk_detect_critical(struct device_node *np, int index, * for improved portability across platforms */ -#if IS_ENABLED(CONFIG_PPC) - -static inline u32 clk_readl(u32 __iomem *reg) -{ - return ioread32be(reg); -} - -static inline void clk_writel(u32 val, u32 __iomem *reg) -{ - iowrite32be(val, reg); -} - -#else /* platform dependent I/O accessors */ - static inline u32 clk_readl(u32 __iomem *reg) { return readl(reg); @@ -1025,8 +1011,6 @@ static inline void clk_writel(u32 val, u32 __iomem *reg) writel(val, reg); } -#endif /* platform dependent I/O accessors */ - void clk_gate_restore_context(struct clk_hw *hw); #endif /* CONFIG_COMMON_CLK */ From patchwork Mon Apr 15 10:10:46 2019 Content-Type: text/plain; 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Mon, 15 Apr 2019 03:11:06 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id d6sm11592214wrp.9.2019.04.15.03.11.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 03:11:05 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Cc: Anatolij Gustschin , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Stuebner , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Michal Simek Subject: [PATCH RFT V2 8/8] clk: core: replace clk_{readl, writel} with {readl, writel} Date: Mon, 15 Apr 2019 12:10:46 +0200 Message-Id: <20190415101046.5872-9-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190415101046.5872-1-jonas.gorski@gmail.com> References: <20190415101046.5872-1-jonas.gorski@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that clk_{readl,writel} is just an alias for {readl,writel}, we can switch all users of clk_* to use the accessors directly and remove the helpers. Signed-off-by: Jonas Gorski --- V1 -> V2: * newly added patch drivers/clk/clk-divider.c | 4 ++-- drivers/clk/clk-fractional-divider.c | 4 ++-- drivers/clk/clk-gate.c | 4 ++-- drivers/clk/clk-multiplier.c | 4 ++-- drivers/clk/clk-mux.c | 4 ++-- drivers/clk/clk-xgene.c | 6 +++--- drivers/clk/hisilicon/clk-hisi-phase.c | 4 ++-- drivers/clk/imx/clk-divider-gate.c | 20 ++++++++++---------- drivers/clk/imx/clk-sccg-pll.c | 12 ++++++------ drivers/clk/nxp/clk-lpc18xx-ccu.c | 6 +++--- drivers/clk/nxp/clk-lpc18xx-cgu.c | 24 ++++++++++++------------ drivers/clk/rockchip/clk-ddr.c | 2 +- drivers/clk/rockchip/clk-half-divider.c | 6 +++--- drivers/clk/tegra/clk-tegra124.c | 4 ++-- drivers/clk/tegra/clk-tegra210.c | 6 +++--- drivers/clk/zynq/clkc.c | 6 +++--- drivers/clk/zynq/pll.c | 18 +++++++++--------- include/linux/clk-provider.h | 15 --------------- 18 files changed, 67 insertions(+), 82 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index ff791a7a5e9e..bb49dbf05a64 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -30,7 +30,7 @@ static inline u32 clk_div_readl(struct clk_divider *divider) if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) return ioread32be(divider->reg); else - return clk_readl(divider->reg); + return readl(divider->reg); } static inline void clk_div_writel(struct clk_divider *divider, u32 val) @@ -38,7 +38,7 @@ static inline void clk_div_writel(struct clk_divider *divider, u32 val) if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) iowrite32be(val, divider->reg); else - clk_writel(val, divider->reg); + writel(val, divider->reg); } #define div_mask(width) ((1 << (width)) - 1) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index b9988d3b3828..99133554466f 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -18,7 +18,7 @@ static inline u32 clk_fd_readl(struct clk_fractional_divider *fd) if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN) return ioread32be(fd->reg); else - return clk_readl(fd->reg); + return readl(fd->reg); } static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val) @@ -26,7 +26,7 @@ static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val) if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN) iowrite32be(val, fd->reg); else - clk_writel(val, fd->reg); + writel(val, fd->reg); } static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 521e112ef5b5..bd201eaa99df 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -28,7 +28,7 @@ static inline u32 clk_gate_readl(struct clk_gate *gate) if (gate->flags & CLK_GATE_BIG_ENDIAN) return ioread32be(gate->reg); else - return clk_readl(gate->reg); + return readl(gate->reg); } static inline void clk_gate_writel(struct clk_gate *gate, u32 val) @@ -36,7 +36,7 @@ static inline void clk_gate_writel(struct clk_gate *gate, u32 val) if (gate->flags & CLK_GATE_BIG_ENDIAN) iowrite32be(val, gate->reg); else - clk_writel(val, gate->reg); + writel(val, gate->reg); } /* diff --git a/drivers/clk/clk-multiplier.c b/drivers/clk/clk-multiplier.c index fb032f7dd407..a433442a1fa6 100644 --- a/drivers/clk/clk-multiplier.c +++ b/drivers/clk/clk-multiplier.c @@ -16,7 +16,7 @@ static inline u32 clk_mult_readl(struct clk_multiplier *mult) if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) return ioread32be(mult->reg); else - return clk_readl(mult->reg); + return readl(mult->reg); } static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val) @@ -24,7 +24,7 @@ static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val) if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN) iowrite32be(val, mult->reg); else - clk_writel(val, mult->reg); + writel(val, mult->reg); } static unsigned long __get_mult(struct clk_multiplier *mult, diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 47f6f4f55f08..9ae3a4c17ed5 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -28,7 +28,7 @@ static inline u32 clk_mux_readl(struct clk_mux *mux) if (mux->flags & CLK_MUX_BIG_ENDIAN) return ioread32be(mux->reg); else - return clk_readl(mux->reg); + return readl(mux->reg); } static inline void clk_mux_writel(struct clk_mux *mux, u32 val) @@ -36,7 +36,7 @@ static inline void clk_mux_writel(struct clk_mux *mux, u32 val) if (mux->flags & CLK_MUX_BIG_ENDIAN) iowrite32be(val, mux->reg); else - clk_writel(val, mux->reg); + writel(val, mux->reg); } int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c index 531b030d4d4e..d975465fe2a8 100644 --- a/drivers/clk/clk-xgene.c +++ b/drivers/clk/clk-xgene.c @@ -262,7 +262,7 @@ static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw, else __acquire(fd->lock); - val = clk_readl(fd->reg); + val = readl(fd->reg); if (fd->lock) spin_unlock_irqrestore(fd->lock, flags); @@ -333,10 +333,10 @@ static int xgene_clk_pmd_set_rate(struct clk_hw *hw, unsigned long rate, else __acquire(fd->lock); - val = clk_readl(fd->reg); + val = readl(fd->reg); val &= ~fd->mask; val |= (scale << fd->shift); - clk_writel(val, fd->reg); + writel(val, fd->reg); if (fd->lock) spin_unlock_irqrestore(fd->lock, flags); diff --git a/drivers/clk/hisilicon/clk-hisi-phase.c b/drivers/clk/hisilicon/clk-hisi-phase.c index 5fdc267bb2da..ba6afad66a2b 100644 --- a/drivers/clk/hisilicon/clk-hisi-phase.c +++ b/drivers/clk/hisilicon/clk-hisi-phase.c @@ -75,10 +75,10 @@ static int hisi_clk_set_phase(struct clk_hw *hw, int degrees) spin_lock_irqsave(phase->lock, flags); - val = clk_readl(phase->reg); + val = readl(phase->reg); val &= ~phase->mask; val |= regval << phase->shift; - clk_writel(val, phase->reg); + writel(val, phase->reg); spin_unlock_irqrestore(phase->lock, flags); diff --git a/drivers/clk/imx/clk-divider-gate.c b/drivers/clk/imx/clk-divider-gate.c index df1f8429fe16..2a8352a316c7 100644 --- a/drivers/clk/imx/clk-divider-gate.c +++ b/drivers/clk/imx/clk-divider-gate.c @@ -29,7 +29,7 @@ static unsigned long clk_divider_gate_recalc_rate_ro(struct clk_hw *hw, struct clk_divider *div = to_clk_divider(hw); unsigned int val; - val = clk_readl(div->reg) >> div->shift; + val = readl(div->reg) >> div->shift; val &= clk_div_mask(div->width); if (!val) return 0; @@ -51,7 +51,7 @@ static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw, if (!clk_hw_is_enabled(hw)) { val = div_gate->cached_val; } else { - val = clk_readl(div->reg) >> div->shift; + val = readl(div->reg) >> div->shift; val &= clk_div_mask(div->width); } @@ -87,10 +87,10 @@ static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate, spin_lock_irqsave(div->lock, flags); if (clk_hw_is_enabled(hw)) { - val = clk_readl(div->reg); + val = readl(div->reg); val &= ~(clk_div_mask(div->width) << div->shift); val |= (u32)value << div->shift; - clk_writel(val, div->reg); + writel(val, div->reg); } else { div_gate->cached_val = value; } @@ -114,9 +114,9 @@ static int clk_divider_enable(struct clk_hw *hw) spin_lock_irqsave(div->lock, flags); /* restore div val */ - val = clk_readl(div->reg); + val = readl(div->reg); val |= div_gate->cached_val << div->shift; - clk_writel(val, div->reg); + writel(val, div->reg); spin_unlock_irqrestore(div->lock, flags); @@ -133,10 +133,10 @@ static void clk_divider_disable(struct clk_hw *hw) spin_lock_irqsave(div->lock, flags); /* store the current div val */ - val = clk_readl(div->reg) >> div->shift; + val = readl(div->reg) >> div->shift; val &= clk_div_mask(div->width); div_gate->cached_val = val; - clk_writel(0, div->reg); + writel(0, div->reg); spin_unlock_irqrestore(div->lock, flags); } @@ -146,7 +146,7 @@ static int clk_divider_is_enabled(struct clk_hw *hw) struct clk_divider *div = to_clk_divider(hw); u32 val; - val = clk_readl(div->reg) >> div->shift; + val = readl(div->reg) >> div->shift; val &= clk_div_mask(div->width); return val ? 1 : 0; @@ -206,7 +206,7 @@ struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name, div_gate->divider.hw.init = &init; div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags; /* cache gate status */ - val = clk_readl(reg) >> shift; + val = readl(reg) >> shift; val &= clk_div_mask(width); div_gate->cached_val = val; diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c index 9dfd03a95557..991bbe63f156 100644 --- a/drivers/clk/imx/clk-sccg-pll.c +++ b/drivers/clk/imx/clk-sccg-pll.c @@ -348,7 +348,7 @@ static unsigned long clk_sccg_pll_recalc_rate(struct clk_hw *hw, temp64 = parent_rate; - val = clk_readl(pll->base + PLL_CFG0); + val = readl(pll->base + PLL_CFG0); if (val & SSCG_PLL_BYPASS2_MASK) { temp64 = parent_rate; } else if (val & SSCG_PLL_BYPASS1_MASK) { @@ -371,10 +371,10 @@ static int clk_sccg_pll_set_rate(struct clk_hw *hw, unsigned long rate, u32 val; /* set bypass here too since the parent might be the same */ - val = clk_readl(pll->base + PLL_CFG0); + val = readl(pll->base + PLL_CFG0); val &= ~SSCG_PLL_BYPASS_MASK; val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass); - clk_writel(val, pll->base + PLL_CFG0); + writel(val, pll->base + PLL_CFG0); val = readl_relaxed(pll->base + PLL_CFG2); val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK); @@ -395,7 +395,7 @@ static u8 clk_sccg_pll_get_parent(struct clk_hw *hw) u32 val; u8 ret = pll->parent; - val = clk_readl(pll->base + PLL_CFG0); + val = readl(pll->base + PLL_CFG0); if (val & SSCG_PLL_BYPASS2_MASK) ret = pll->bypass2; else if (val & SSCG_PLL_BYPASS1_MASK) @@ -408,10 +408,10 @@ static int clk_sccg_pll_set_parent(struct clk_hw *hw, u8 index) struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); u32 val; - val = clk_readl(pll->base + PLL_CFG0); + val = readl(pll->base + PLL_CFG0); val &= ~SSCG_PLL_BYPASS_MASK; val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass); - clk_writel(val, pll->base + PLL_CFG0); + writel(val, pll->base + PLL_CFG0); return clk_sccg_pll_wait_lock(pll); } diff --git a/drivers/clk/nxp/clk-lpc18xx-ccu.c b/drivers/clk/nxp/clk-lpc18xx-ccu.c index 27781b49eb82..5969f620607a 100644 --- a/drivers/clk/nxp/clk-lpc18xx-ccu.c +++ b/drivers/clk/nxp/clk-lpc18xx-ccu.c @@ -142,7 +142,7 @@ static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable) * Divider field is write only, so divider stat field must * be read so divider field can be set accordingly. */ - val = clk_readl(gate->reg); + val = readl(gate->reg); if (val & LPC18XX_CCU_DIVSTAT) val |= LPC18XX_CCU_DIV; @@ -155,12 +155,12 @@ static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable) * and the next write should clear the RUN bit. */ val |= LPC18XX_CCU_AUTO; - clk_writel(val, gate->reg); + writel(val, gate->reg); val &= ~LPC18XX_CCU_RUN; } - clk_writel(val, gate->reg); + writel(val, gate->reg); return 0; } diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c index 2531174b399e..f5bc8bd192b7 100644 --- a/drivers/clk/nxp/clk-lpc18xx-cgu.c +++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c @@ -352,9 +352,9 @@ static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw, struct lpc18xx_pll *pll = to_lpc_pll(hw); u32 ctrl, mdiv, msel, npdiv; - ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); - mdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV); - npdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); + ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); + mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV); + npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); if (ctrl & LPC18XX_PLL0_CTRL_BYPASS) return parent_rate; @@ -415,25 +415,25 @@ static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate, m |= lpc18xx_pll0_msel2seli(m) << LPC18XX_PLL0_MDIV_SELI_SHIFT; /* Power down PLL, disable clk output and dividers */ - ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); + ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); ctrl |= LPC18XX_PLL0_CTRL_PD; ctrl &= ~(LPC18XX_PLL0_CTRL_BYPASS | LPC18XX_PLL0_CTRL_DIRECTI | LPC18XX_PLL0_CTRL_DIRECTO | LPC18XX_PLL0_CTRL_CLKEN); - clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); + writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); /* Configure new PLL settings */ - clk_writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV); - clk_writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); + writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV); + writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); /* Power up PLL and wait for lock */ ctrl &= ~LPC18XX_PLL0_CTRL_PD; - clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); + writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); do { udelay(10); - stat = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT); + stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT); if (stat & LPC18XX_PLL0_STAT_LOCK) { ctrl |= LPC18XX_PLL0_CTRL_CLKEN; - clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); + writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); return 0; } @@ -458,8 +458,8 @@ static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw, bool direct, fbsel; u32 stat, ctrl; - stat = clk_readl(pll->reg + LPC18XX_CGU_PLL1_STAT); - ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL1_CTRL); + stat = readl(pll->reg + LPC18XX_CGU_PLL1_STAT); + ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL); direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false; fbsel = (ctrl & LPC18XX_PLL1_CTRL_FBSEL) ? true : false; diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index ebce5260068b..09ede6920593 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -82,7 +82,7 @@ static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw) struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw); u32 val; - val = clk_readl(ddrclk->reg_base + + val = readl(ddrclk->reg_base + ddrclk->mux_offset) >> ddrclk->mux_shift; val &= GENMASK(ddrclk->mux_width - 1, 0); diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c index b8da6e799423..784b81e1ea7c 100644 --- a/drivers/clk/rockchip/clk-half-divider.c +++ b/drivers/clk/rockchip/clk-half-divider.c @@ -24,7 +24,7 @@ static unsigned long clk_half_divider_recalc_rate(struct clk_hw *hw, struct clk_divider *divider = to_clk_divider(hw); unsigned int val; - val = clk_readl(divider->reg) >> divider->shift; + val = readl(divider->reg) >> divider->shift; val &= div_mask(divider->width); val = val * 2 + 3; @@ -124,11 +124,11 @@ static int clk_half_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { val = div_mask(divider->width) << (divider->shift + 16); } else { - val = clk_readl(divider->reg); + val = readl(divider->reg); val &= ~(div_mask(divider->width) << divider->shift); } val |= value << divider->shift; - clk_writel(val, divider->reg); + writel(val, divider->reg); if (divider->lock) spin_unlock_irqrestore(divider->lock, flags); diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index df0018f7bf7e..abc0c4bea740 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1466,9 +1466,9 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np) tegra_pmc_clk_init(pmc_base, tegra124_clks); /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */ - plld_base = clk_readl(clk_base + PLLD_BASE); + plld_base = readl(clk_base + PLLD_BASE); plld_base &= ~BIT(25); - clk_writel(plld_base, clk_base + PLLD_BASE); + writel(plld_base, clk_base + PLLD_BASE); } /** diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 7545af763d7a..ed3c7df75d1e 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3557,7 +3557,7 @@ static void __init tegra210_clock_init(struct device_node *np) if (!clks) return; - value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT; + value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT; clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1; if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq, @@ -3574,9 +3574,9 @@ static void __init tegra210_clock_init(struct device_node *np) tegra_pmc_clk_init(pmc_base, tegra210_clks); /* For Tegra210, PLLD is the only source for DSIA & DSIB */ - value = clk_readl(clk_base + PLLD_BASE); + value = readl(clk_base + PLLD_BASE); value &= ~BIT(25); - clk_writel(value, clk_base + PLLD_BASE); + writel(value, clk_base + PLLD_BASE); tegra_clk_apply_init_table = tegra210_clock_apply_init_table; diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index d7b53ac8ad11..4b9d5c14c400 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -158,7 +158,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk, clks[fclk] = clk_register_gate(NULL, clk_name, div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); - enable_reg = clk_readl(fclk_gate_reg) & 1; + enable_reg = readl(fclk_gate_reg) & 1; if (enable && !enable_reg) { if (clk_prepare_enable(clks[fclk])) pr_warn("%s: FCLK%u enable failed\n", __func__, @@ -287,7 +287,7 @@ static void __init zynq_clk_setup(struct device_node *np) SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); /* CPU clocks */ - tmp = clk_readl(SLCR_621_TRUE) & 1; + tmp = readl(SLCR_621_TRUE) & 1; clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock); @@ -510,7 +510,7 @@ static void __init zynq_clk_setup(struct device_node *np) &dbgclk_lock); /* leave debug clocks in the state the bootloader set them up to */ - tmp = clk_readl(SLCR_DBG_CLK_CTRL); + tmp = readl(SLCR_DBG_CLK_CTRL); if (tmp & DBG_CLK_CTRL_CLKACT_TRC) if (clk_prepare_enable(clks[dbg_trc])) pr_warn("%s: trace clk enable failed\n", __func__); diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c index 00d72fb5c036..800b70ee19b3 100644 --- a/drivers/clk/zynq/pll.c +++ b/drivers/clk/zynq/pll.c @@ -90,7 +90,7 @@ static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw, * makes probably sense to redundantly save fbdiv in the struct * zynq_pll to save the IO access. */ - fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> + fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; return parent_rate * fbdiv; @@ -112,7 +112,7 @@ static int zynq_pll_is_enabled(struct clk_hw *hw) spin_lock_irqsave(clk->lock, flags); - reg = clk_readl(clk->pll_ctrl); + reg = readl(clk->pll_ctrl); spin_unlock_irqrestore(clk->lock, flags); @@ -138,10 +138,10 @@ static int zynq_pll_enable(struct clk_hw *hw) /* Power up PLL and wait for lock */ spin_lock_irqsave(clk->lock, flags); - reg = clk_readl(clk->pll_ctrl); + reg = readl(clk->pll_ctrl); reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK); - clk_writel(reg, clk->pll_ctrl); - while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit))) + writel(reg, clk->pll_ctrl); + while (!(readl(clk->pll_status) & (1 << clk->lockbit))) ; spin_unlock_irqrestore(clk->lock, flags); @@ -168,9 +168,9 @@ static void zynq_pll_disable(struct clk_hw *hw) /* shut down PLL */ spin_lock_irqsave(clk->lock, flags); - reg = clk_readl(clk->pll_ctrl); + reg = readl(clk->pll_ctrl); reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK; - clk_writel(reg, clk->pll_ctrl); + writel(reg, clk->pll_ctrl); spin_unlock_irqrestore(clk->lock, flags); } @@ -223,9 +223,9 @@ struct clk *clk_register_zynq_pll(const char *name, const char *parent, spin_lock_irqsave(pll->lock, flags); - reg = clk_readl(pll->pll_ctrl); + reg = readl(pll->pll_ctrl); reg &= ~PLLCTRL_BPQUAL_MASK; - clk_writel(reg, pll->pll_ctrl); + writel(reg, pll->pll_ctrl); spin_unlock_irqrestore(pll->lock, flags); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 479e616ce7f5..46d5fc3057b5 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -996,21 +996,6 @@ static inline int of_clk_detect_critical(struct device_node *np, int index, } #endif /* CONFIG_OF */ -/* - * wrap access to peripherals in accessor routines - * for improved portability across platforms - */ - -static inline u32 clk_readl(u32 __iomem *reg) -{ - return readl(reg); -} - -static inline void clk_writel(u32 val, u32 __iomem *reg) -{ - writel(val, reg); -} - void clk_gate_restore_context(struct clk_hw *hw); #endif /* CONFIG_COMMON_CLK */