From patchwork Thu Apr 11 10:57:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1083896 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="m+CPze15"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fyRs3PRxz9s7h for ; Thu, 11 Apr 2019 20:48:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726588AbfDKKrj (ORCPT ); Thu, 11 Apr 2019 06:47:39 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:40745 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726615AbfDKKrj (ORCPT ); Thu, 11 Apr 2019 06:47:39 -0400 Received: by mail-wm1-f67.google.com with SMTP id z24so6085036wmi.5; Thu, 11 Apr 2019 03:47:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1WIGTjZh4mIwUZpoXVfzkYofixlglZX9sKei53EYiYk=; b=m+CPze15BXpmCnfHe7tC+npflErN9n978bF/GtAZ/nX87YZWIgkaiMAFrwvD1Nrjy+ qlVaufbg7pJdUuYiibezwwJXcrv74A9kcUAJzI3Ir4CxYK5U815wQg3BO+aYXb712Zic EO7sNsV7fylxIQ4eTCq5aFi7Tj3AHGdVCjB8dNPf05XaDD0I5YHFoc+m0WfI5wYuP+6O iRfkka8jrKWj3VtFFiXQz1GzO95TsPBeo1xH7lTTR6jbTTw3wUsGelJEupKeedmQs4fL Jc0tWoQK3mtQ/oVVMwJy3m04B0HnJZhHVDZEprSuYTDsCwKTNyv1RRA4BXqmZAdryTxk 0afw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1WIGTjZh4mIwUZpoXVfzkYofixlglZX9sKei53EYiYk=; b=YVbXiRbR+iw9h1clW+8FHhh6mZRaS1lc6tw9s/CU7HcqQR7M17jwPCGjhw8bbGdFaz O/fgtHqoGjH3l5mPaoOI29hFAC+rERsKzyJYhlLnNPHXG2F6v/AWKTgyOmVywrUya5US rBGpDqIy7bNKKb/K5Tod60uxbeiUraZkRP8VU2+Zs5LXA99Ql9Hu6SqhxpI3dslyfs8q bd59tfLszA5fon4MYWJxVWHHEiMa+gQr+8YNmN4Yx2ljhzMlULkfAHJi/TTs2dss4tYb gVrDjhvusc3r8fX0Bh7Sjbi5U9olPHVpm7OPDzpy8R6E4htq55raix4HjrRUYdPDXF1Y L7/w== X-Gm-Message-State: APjAAAVrG6+gdmOr/2fkd8SonEifxV8ozLjO3oohUFIb/RIz5eCMAQn/ NOu1SkUKutRkDM/iTBbcd1E= X-Google-Smtp-Source: APXvYqypVQbIptRxZbWO4OESOGCBjxgP1jLmEUbZYgewaa0EuMPpeITisCxAjn+XI/8xMN4HpeSQVw== X-Received: by 2002:a1c:e912:: with SMTP id q18mr5976460wmc.137.1554979657350; Thu, 11 Apr 2019 03:47:37 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::df7e:4a05]) by smtp.gmail.com with ESMTPSA id k4sm54987587wro.33.2019.04.11.03.47.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Apr 2019 03:47:36 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jagan Teki , Jernej Skrabec Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, Neil Armstrong , Kevin Hilman Subject: [PATCH v2 1/8] dt-bindings: gpu: mali-midgard: Add resets property Date: Thu, 11 Apr 2019 12:57:13 +0200 Message-Id: <20190411105720.32357-2-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190411105720.32357-1-peron.clem@gmail.com> References: <20190411105720.32357-1-peron.clem@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Neil Armstrong The Amlogic ARM Mali Midgard requires reset controls to power on and software reset the GPU, adds these as optional in the bindings. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 18a2cde2e5f3..1b1a74129141 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -37,6 +37,20 @@ Optional properties: - operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt for details. +- resets : Phandle of the GPU reset line. + +Vendor-specific bindings +------------------------ + +The Mali GPU is integrated very differently from one SoC to +another. In order to accomodate those differences, you have the option +to specify one more vendor-specific compatible, among: + +- "amlogic,meson-gxm-mali" + Required properties: + - resets : Should contain phandles of : + + GPU reset line + + GPU APB glue reset line Example for a Mali-T760: From patchwork Thu Apr 11 10:57:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1083893 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OoNxAH/U"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fyRg3QHrz9s00 for ; Thu, 11 Apr 2019 20:48:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726851AbfDKKro (ORCPT ); Thu, 11 Apr 2019 06:47:44 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:41910 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726798AbfDKKrk (ORCPT ); Thu, 11 Apr 2019 06:47:40 -0400 Received: by mail-wr1-f65.google.com with SMTP id r4so6665796wrq.8; Thu, 11 Apr 2019 03:47:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0qACYbWibCn2NYEQtyoZ/KKRf3EQ91V9nFYFBIMWmRE=; b=OoNxAH/UfZWQ71k0iVbW+Nd4KZMUclCIEDuHnjYtLfggWsktEQj8t5eyskGK4f57o9 rYDvKldzHFOtrFQSkXlXSHSFl4AP8Q6cHOgeLrzGESILvkJF6bF0KQtENGLoPxXpawwS ed82nuuJrmOgmtbDYT2vjKudiEGYDkXCfpUadAHZiKShGQtYZ6bfbSdIjTOZk3XebqIm xRONMSLQamIk6yBwYXV1iZxqIOWo2XzGpDxMdFpRbsvKEs13PPFOHBp/o/bSsFne2kjw uGNBpi1HUbATtdkZ+JNuaqQYT00evBBO4aEwIpbcXnKgNtmoWCkm+Klp8DEbjRcODQLS kr9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0qACYbWibCn2NYEQtyoZ/KKRf3EQ91V9nFYFBIMWmRE=; b=s08YPKEDC152uhU0quyv93R+Fd40FuD7OypGH96zuW6dxB5gpkoTVvhWLYdu275D5m pcwTBhYUPVoFwF4eKeb3YaA5EafeON+IhZMM+BNhAK9owYsxPlY9yEDkf/7xL0Lj7dKc JrrbrSC4EF5ZB8Ql+76VboYst7OjiMpUCdKtZ4p9n1i03l0w9u9VbZ0XT6sonvxB6JQW BMavLH6IuD27clhJ94gK6JTBLRucNqg86EZYPkMUkSlbimRQm43efrsMDGV68VCMJdNc 6N8/X/DnfWl8WGAxJbTnteRlgr7u/yavIyjP34RDnvU7wihzihjJsVshDGedol18J3ug Ub/g== X-Gm-Message-State: APjAAAUxcPBdpqJW5pZ7m6JY2sJt+KZsn5fFDaXlgyD93PsS6BQbqI0e 5bt+WbXMmPc0faObvl9T+J0= X-Google-Smtp-Source: APXvYqy9Ffo+bDiYwpkeZxK/eC2sbRafYMnlCEqnhKorcJATkTITXvDg3unrBdUlj+ef9w8kjCE75g== X-Received: by 2002:adf:dc88:: with SMTP id r8mr8993988wrj.28.1554979658424; Thu, 11 Apr 2019 03:47:38 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::df7e:4a05]) by smtp.gmail.com with ESMTPSA id k4sm54987587wro.33.2019.04.11.03.47.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Apr 2019 03:47:37 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jagan Teki , Jernej Skrabec Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v2 2/8] dt-bindings: gpu: add bus clock for Mali Midgard GPUs Date: Thu, 11 Apr 2019 12:57:14 +0200 Message-Id: <20190411105720.32357-3-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190411105720.32357-1-peron.clem@gmail.com> References: <20190411105720.32357-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some SoCs adds a bus clock gate to the Mali Midgard GPU. Add the binding for the bus clock. Signed-off-by: Icenowy Zheng Signed-off-by: Clément Péron --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 1b1a74129141..2e8bbce35695 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -31,6 +31,12 @@ Optional properties: - clocks : Phandle to clock for the Mali Midgard device. +- clock-names : Specify the names of the clocks specified in clocks + when multiple clocks are present. + * core: clock driving the GPU itself (When only one clock is present, + assume it's this clock.) + * bus: bus clock for the GPU + - mali-supply : Phandle to regulator for the Mali device. Refer to Documentation/devicetree/bindings/regulator/regulator.txt for details. From patchwork Thu Apr 11 10:57:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1083889 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="DCvh5DJN"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44fyR51BxRz9s71 for ; Thu, 11 Apr 2019 20:47:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726842AbfDKKrn (ORCPT ); Thu, 11 Apr 2019 06:47:43 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:40752 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726615AbfDKKrm (ORCPT ); Thu, 11 Apr 2019 06:47:42 -0400 Received: by mail-wm1-f68.google.com with SMTP id z24so6085219wmi.5; Thu, 11 Apr 2019 03:47:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JHkOGE5uu1KF72uJBHM3+EVdhQraRuZIRYHO0QubjyY=; b=DCvh5DJN/VhCX8twV583hUuNgsfSrt4arzUvg9WdmDMr4gFsPQIZP5S3N4KtF8fJYt 99FymPlUe6sGtGWuF0O/vszLfuObtYKWss7mpmGWX9QiKsG5MONdbP9uDotpKYKg+ess yB/nP3dNHfZ7R659mVg3LLeDRLKWdVm01qIs/sjjUJn3MflWG7rMesrUlf4fUR0P71bi tqRO7He6L2ekx/Fk1naW5mBTywUF6xXN+WS2EwJNm8V1kwg7rWaooO4gdZX7ecEHTrVk 3G65jbB06ogBj/uHJ/PebdGwMUDowbQOz1T6RehMQluJYaEkBA441JSKwmRhbjt2UfIs v91A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JHkOGE5uu1KF72uJBHM3+EVdhQraRuZIRYHO0QubjyY=; b=ElgorAhM8tIpbEx3+dHjI4zsvfIEdSKkyboThwURNqrnfI722Q/DjtNyDEbv0HdmK3 8btun5KkUtaqiPKdZhqNMVqBrXBCVrNgJt5F4I21908SgDlBkPNcmjyM7pp3OIy7rMiX mqtU3I+hDmxCQnTphSMmyvjlUZj9RvmD8Ju5Gq6nEled94WLUvuO1SNT+YODNI/1oaUJ rdLpiB5koofDeLL6FHcFI28oOOmBAJ6vBDxCrx568EsH0td8MQkIfFSxfe47Wm7+ILCd LwNPwlya6cbj4sJ/DzR+sf6cmMYtVWfB1VPynqI1R56y0Ue9kqAXKo1b3/KOuzyet+Zn 7+kA== X-Gm-Message-State: APjAAAXl6qo7HbZaB7KG42p5JHPZHK/BVumsIovRyUgZalpaybv7Ge0s o72Psb3essojQ3Lb+g1DeHY= X-Google-Smtp-Source: APXvYqwUVO47Xzv2wwLZM5mMaymg37EacWx0IUtmMP2cUVDdxOkoyVaeBEJxOwxhGQeCdikT5Puxqg== X-Received: by 2002:a1c:67c1:: with SMTP id b184mr5906273wmc.12.1554979659783; Thu, 11 Apr 2019 03:47:39 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::df7e:4a05]) by smtp.gmail.com with ESMTPSA id k4sm54987587wro.33.2019.04.11.03.47.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Apr 2019 03:47:38 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jagan Teki , Jernej Skrabec Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v2 3/8] dt-bindings: gpu: mali-midgard: Add h6 mali gpu compatible Date: Thu, 11 Apr 2019 12:57:15 +0200 Message-Id: <20190411105720.32357-4-peron.clem@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190411105720.32357-1-peron.clem@gmail.com> References: <20190411105720.32357-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This add the H6 mali compatible in the dt-bindings to later support specific implementation. Signed-off-by: Clément Péron --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 2e8bbce35695..0000ec4a9f44 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -15,6 +15,7 @@ Required properties: + "arm,mali-t860" + "arm,mali-t880" * which must be preceded by one of the following vendor specifics: + + "allwinner,sun50i-h6-mali" + "amlogic,meson-gxm-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" @@ -49,9 +50,15 @@ Vendor-specific bindings ------------------------ The Mali GPU is integrated very differently from one SoC to -another. In order to accomodate those differences, you have the option +another. In order to accommodate those differences, you have the option to specify one more vendor-specific compatible, among: +- "allwinner,sun50i-h6-mali" + Required properties: + - clocks : phandles to core and bus clocks + - clock-names : must contain "core" and "bus" + - resets: phandle to GPU reset line + - "amlogic,meson-gxm-mali" Required properties: - resets : Should contain phandles of :