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Wed, 10 Apr 2019 15:03:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector1-marvell-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BFmpzAMhO6j05OOMTrCr9BGuvHnVAro/C4SBD32Fse4=; b=CqefMZTcJv3pk/gg+SooI+7LJAKqZlssE6QH3DmnkbdBG3eDKOpA7eIwO0ekn+FDyRGUhiU0NOkFGgfC8p+SoJr6wfYSFKEDxuI3uRmvHP66pBINKwz3bX6Gt38zmkNRGeIR5Ymihf3e2M852l1T0KASfCf9ZWN6biTVAgSQiOY= Received: from BN6PR1801MB2033.namprd18.prod.outlook.com (10.161.154.24) by BN6PR1801MB2036.namprd18.prod.outlook.com (10.161.156.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.16; Wed, 10 Apr 2019 22:03:23 +0000 Received: from BN6PR1801MB2033.namprd18.prod.outlook.com ([fe80::c529:5a78:cc80:7112]) by BN6PR1801MB2033.namprd18.prod.outlook.com ([fe80::c529:5a78:cc80:7112%4]) with mapi id 15.20.1771.016; Wed, 10 Apr 2019 22:03:23 +0000 From: Steve Ellcey To: "gcc-patches@gcc.gnu.org" , "Marcus.Shawcroft@arm.com" , "james.greenhalgh@arm.com" , "Richard.Earnshaw@arm.com" , "tamar.christina@arm.com" Subject: [Patch] [Aarch64] PR rtl-optimization/87763 - this patch fixes gcc.target/aarch64/lsl_asr_sbfiz.c Date: Wed, 10 Apr 2019 22:03:23 +0000 Message-ID: <78cb6082e68ed593a8e247c295ff3c415c2194ac.camel@marvell.com> received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 Content-ID: <868E0F3F0AE20247891CD8C8BD61D93C@namprd18.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED Here is another patch to fix one of the failures listed in PR rtl-optimization/87763. This change fixes gcc.target/aarch64/lsl_asr_sbfiz.c by adding an alternative version of *ashiftsi_extv_bfiz that has a subreg in it. Tested with bootstrap and regression test run. OK for checkin? Steve Ellcey 2018-04-10 Steve Ellcey PR rtl-optimization/87763 * config/aarch64/aarch64.md (*ashiftsi_extv_bfiz_alt): New Instruction. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index e0df975..04dc06f 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5634,6 +5634,22 @@ [(set_attr "type" "bfx")] ) +(define_insn "*ashiftsi_extv_bfiz_alt" + [(set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI + (subreg:SI + (sign_extract:DI + (subreg:DI (match_operand:SI 1 "register_operand" "r") 0) + (match_operand 2 "aarch64_simd_shift_imm_offset_si" "n") + (const_int 0)) + 0) + (match_operand 3 "aarch64_simd_shift_imm_si" "n")))] + "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]), + 1, GET_MODE_BITSIZE (SImode) - 1)" + "sbfiz\\t%w0, %w1, %3, %2" + [(set_attr "type" "bfx")] +) + ;; When the bit position and width of the equivalent extraction add up to 32 ;; we can use a W-reg LSL instruction taking advantage of the implicit ;; zero-extension of the X-reg.