From patchwork Thu Apr 4 11:59:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077183 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Mj6jJTuc"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44ZhMh1yrzz9sPf for ; Thu, 4 Apr 2019 22:59:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 45D05C21E07; Thu, 4 Apr 2019 11:59:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 98508C21DB3; Thu, 4 Apr 2019 11:59:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EA16AC21C3F; Thu, 4 Apr 2019 11:59:48 +0000 (UTC) Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by lists.denx.de (Postfix) with ESMTPS id A19CAC21C29 for ; Thu, 4 Apr 2019 11:59:48 +0000 (UTC) Received: by mail-wr1-f66.google.com with SMTP id j9so3433773wrn.6 for ; Thu, 04 Apr 2019 04:59:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L/NTSabc4kajkmaxDsMs8kLL3mmvHKRVEZHaVolP2JM=; b=Mj6jJTucUlehGrskSuSr35otfAB5aq1sukl9wB65E+HUxggl1/dXZfDtCwCWxkPl6I Vtl/xtbsSPayKaHFlN2iiIk0rLhFSByz485z5FXjE/jnibQc7qBEgVn8jDciOgt1q80a OeLIdIgc7F1GS6HwmPsjSLKJGTiLBw1BmHEiOoFQoQRsjOvJUS9yb5k0FcH9nkSTuPmC Szlgk2+DfRE9VpmL/o6x3FU/5/SyhySWNccTVE3glD2I3CZWZ5xEEqXqA61pDaFfdNF7 RDHTs6d2QyP7XojBrBiMLcAgihyPhYX6TNJHnMvRotC3OrslKnhR5ZrYYj31SHSqBrED Euqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L/NTSabc4kajkmaxDsMs8kLL3mmvHKRVEZHaVolP2JM=; b=kOzZieUNx1gtL5fjW4uFLYIYTPhZwTTjKcnZEqmT5uKW1b685jqbsWWNvFAEAFnwW8 GWXbWbQCHfgzTkIEhKuPufQyfuetq2u096G32HiEb6eM5dAZvaOalna9y92k5Z+hvsnf C+4EML1DiA0wlCa7ct+Be8t7bT+HHy/5aHKDhlQI/Wq9Xst0lAmCJoY14a9ZcSsYaERn 2zvykSHaHz16jhJPo4bz2zCbEtWbn62hj+d2YWc57gGn28z+x6X/3djHiu+JdWOoAuf9 ROLt8VNsFM3rmrnXgIS1a7iVuG3lndk4/EgCk2JCZssBoEFcEIaTvMZ8LnqHfcZ+tOV/ 1M3Q== X-Gm-Message-State: APjAAAU33goeUBKfZ7uT+Ihi1H+YyqO0d+UUVCO62+eVPwgbMK3x1J11 0Zu2Q76PLJ0Np7K41lHmlo4= X-Google-Smtp-Source: APXvYqxWq2VSEtH33Dpp+JlGVDQyYuOpYl6FKUZ+LZiO8VBapJJ2E8FaUou5aP24f8Y8MtD4rhpElg== X-Received: by 2002:a05:6000:5:: with SMTP id h5mr3796453wrx.271.1554379188182; Thu, 04 Apr 2019 04:59:48 -0700 (PDT) Received: from localhost (pD9E51B25.dip0.t-ipconnect.de. [217.229.27.37]) by smtp.gmail.com with ESMTPSA id o4sm39263242wmo.20.2019.04.04.04.59.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 04:59:47 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:24 +0200 Message-Id: <20190404115942.17947-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 01/19] ARM: tegra: Use common header for PMU declarations X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding There's no need to replicate the pmu.h header file for every Tegra SoC generation. Use a single header that is shared across generations. Signed-off-by: Thierry Reding --- .../include/asm/{arch-tegra20 => arch-tegra}/pmu.h | 6 +++--- arch/arm/include/asm/arch-tegra114/pmu.h | 12 ------------ arch/arm/include/asm/arch-tegra124/pmu.h | 13 ------------- arch/arm/include/asm/arch-tegra210/pmu.h | 13 ------------- arch/arm/include/asm/arch-tegra30/pmu.h | 12 ------------ arch/arm/mach-tegra/board2.c | 2 +- arch/arm/mach-tegra/emc.c | 2 +- 7 files changed, 5 insertions(+), 55 deletions(-) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/pmu.h (73%) delete mode 100644 arch/arm/include/asm/arch-tegra114/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra124/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra210/pmu.h delete mode 100644 arch/arm/include/asm/arch-tegra30/pmu.h diff --git a/arch/arm/include/asm/arch-tegra20/pmu.h b/arch/arm/include/asm/arch-tegra/pmu.h similarity index 73% rename from arch/arm/include/asm/arch-tegra20/pmu.h rename to arch/arm/include/asm/arch-tegra/pmu.h index 18766dfed2bb..e850875d3166 100644 --- a/arch/arm/include/asm/arch-tegra20/pmu.h +++ b/arch/arm/include/asm/arch-tegra/pmu.h @@ -4,10 +4,10 @@ * NVIDIA Corporation */ -#ifndef _ARCH_PMU_H_ -#define _ARCH_PMU_H_ +#ifndef _TEGRA_PMU_H_ +#define _TEGRA_PMU_H_ /* Set core and CPU voltages to nominal levels */ int pmu_set_nominal(void); -#endif /* _ARCH_PMU_H_ */ +#endif /* _TEGRA_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/pmu.h b/arch/arm/include/asm/arch-tegra114/pmu.h deleted file mode 100644 index 1e571ee7b317..000000000000 --- a/arch/arm/include/asm/arch-tegra114/pmu.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA114_PMU_H_ -#define _TEGRA114_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA114_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pmu.h b/arch/arm/include/asm/arch-tegra124/pmu.h deleted file mode 100644 index c38393edefda..000000000000 --- a/arch/arm/include/asm/arch-tegra124/pmu.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation - */ - -#ifndef _TEGRA124_PMU_H_ -#define _TEGRA124_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA124_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/pmu.h b/arch/arm/include/asm/arch-tegra210/pmu.h deleted file mode 100644 index 6ea36aa41876..000000000000 --- a/arch/arm/include/asm/arch-tegra210/pmu.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2015 - * NVIDIA Corporation - */ - -#ifndef _TEGRA210_PMU_H_ -#define _TEGRA210_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA210_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/pmu.h b/arch/arm/include/asm/arch-tegra30/pmu.h deleted file mode 100644 index a823f0fbfc61..000000000000 --- a/arch/arm/include/asm/arch-tegra30/pmu.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA30_PMU_H_ -#define _TEGRA30_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _TEGRA30_PMU_H_ */ diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 12257a42b51b..b8d5ef0322cb 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -24,7 +25,6 @@ #include #include #include -#include #include #ifdef CONFIG_TEGRA_CLOCK_SCALING #include diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c index 6697909d9a3e..66628933b653 100644 --- a/arch/arm/mach-tegra/emc.c +++ b/arch/arm/mach-tegra/emc.c @@ -8,10 +8,10 @@ #include #include #include -#include #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; From patchwork Thu Apr 4 11:59:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077185 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="AzGrdyWx"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44ZhPc06rfz9sPd for ; Thu, 4 Apr 2019 23:01:39 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 98153C21E56; Thu, 4 Apr 2019 12:00:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8FA5AC21E2B; Thu, 4 Apr 2019 11:59:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 56FAEC21DA2; Thu, 4 Apr 2019 11:59:50 +0000 (UTC) Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by lists.denx.de (Postfix) with ESMTPS id 121FAC21C29 for ; Thu, 4 Apr 2019 11:59:50 +0000 (UTC) Received: by mail-wm1-f67.google.com with SMTP id z11so2752534wmi.0 for ; Thu, 04 Apr 2019 04:59:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VCExboGpnJBwA5UKrrwS2EGHmVJ2i4D8u9whTt+qAow=; b=AzGrdyWxiXFHfTTqBMXojuMY6p5aRWnFum+SFknju+erQAFE9MatuKha/vq2ZBtCMb GZs/XThRVaV8M/s+3pvnXuk7naC68qIfuxZYmttinmm5b1sS49D7xfwEJkxHArp2LaIz dLRYOD2r8PrfJHd97hBSF6KE6+5yeaQ9IMhH2S5VDdznQucG1lpb4Z8rh3Kw73NELErb h0u9X5f7JrB3lKnsfC1rduVJ6Q6RiDLS6guYkIjRnTlyvX0Mcs4GEY9QOQoXef2qfnwL hRn6y0Tl71oZh5F9Pn94W822Pa8IIsdkNf+NVDW1GuadCXxrMqfju2i22Z2nO24LdIrl lQTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VCExboGpnJBwA5UKrrwS2EGHmVJ2i4D8u9whTt+qAow=; b=JggJUhTDn6sl9949sEFe84i112LZSRMyrwvuBUYFmv2Zs9JsLVGrfHpfIjHJRwrFTH n/am1o8N8zNeAYzubhA6A/FUuili6H8wAZj6MVdD6cQ58yWBnIVM9Z4VdWmPykXkxKl6 5DxtRUS58Br9hv9jMeve9nltUxkmgNsmeEeS4K8YqItIxN7URsa4/A/ch2YasrCEBxcV CgYg5UpFaOSEQPd9wmxTNl3AGspggLSxTU/y+3TjeC+IXtX7aydPKVyLh6CH2aVdGVyf Yq0TgV1ZBHGfsqmI5XHTZRzjh8bLWPFaRVLiF9CCJp16mAfsfs4LUy1vNaRpkV/0OMm/ bIWw== X-Gm-Message-State: APjAAAVWY9C9vd9Y3/Ui0SSMP0UY7mU6T8U0d3D7lPR6wzBE+96qTJHU mH3DKJYy6myCifAttO4aNB/w5BqV X-Google-Smtp-Source: APXvYqy+Uu9v5BuMS62dKYwllPd88M5PGfiBo7IroScVBdmrEcuFRZQvy9LheEwl4Lnsw5Z+oaE2Vw== X-Received: by 2002:a7b:c408:: with SMTP id k8mr3896801wmi.69.1554379189641; Thu, 04 Apr 2019 04:59:49 -0700 (PDT) Received: from localhost (pD9E51B25.dip0.t-ipconnect.de. [217.229.27.37]) by smtp.gmail.com with ESMTPSA id o20sm19295700wmh.21.2019.04.04.04.59.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 04:59:49 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:25 +0200 Message-Id: <20190404115942.17947-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 02/19] ARM: tegra: Guard clock code with a Kconfig symbol X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Clock code is not relevant on all Tegra SoC generations, so guard it with a Kconfig symbol that can be selected by the generations that need it. This is in preparation for unifying Tegra186 code with the code used on older generations. Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/Kconfig | 5 +++++ arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/board.c | 2 ++ arch/arm/mach-tegra/board2.c | 12 ++++++++++-- 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 86b1cd11f752..ee078fec9adc 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -12,6 +12,9 @@ config SPL_LIBGENERIC_SUPPORT config SPL_SERIAL_SUPPORT default y +config TEGRA_CLKRST + bool + config TEGRA_IVC bool "Tegra IVC protocol" help @@ -55,6 +58,7 @@ config TEGRA_ARMV7_COMMON select SPL select SPL_BOARD_INIT if SPL select SUPPORT_SPL + select TEGRA_CLKRST select TEGRA_COMMON select TEGRA_GPIO select TEGRA_NO_BPMP @@ -100,6 +104,7 @@ config TEGRA124 config TEGRA210 bool "Tegra210 family" select TEGRA_ARMV8_COMMON + select TEGRA_CLKRST select TEGRA_GPIO select TEGRA_NO_BPMP diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index d4b4666fb1e2..0e812818d7a2 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -16,7 +16,7 @@ endif obj-y += ap.o obj-y += board.o board2.o obj-y += cache.o -obj-y += clock.o +obj-$(CONFIG_TEGRA_CLKRST) += clock.o obj-y += pinmux-common.o obj-y += powergate.o obj-y += xusb-padctl-dummy.o diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index f8fc042a1dcc..ecd5001de4c5 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -9,7 +9,9 @@ #include #include #include +#if IS_ENABLED(CONFIG_TEGRA_CLKRST) #include +#endif #include #include #include diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index b8d5ef0322cb..b94077221f77 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -22,7 +22,9 @@ #include #include #include +#if IS_ENABLED(CONFIG_TEGRA_CLKRST) #include +#endif #include #include #include @@ -109,8 +111,10 @@ int board_init(void) __maybe_unused int board_id; /* Do clocks and UART first so that printf() works */ +#if IS_ENABLED(CONFIG_TEGRA_CLKRST) clock_init(); clock_verify(); +#endif tegra_gpu_config(); @@ -181,8 +185,10 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); int board_early_init_f(void) { +#if IS_ENABLED(CONFIG_TEGRA_CLKRST) if (!clock_early_init_done()) clock_early_init(); +#endif #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) #define USBCMD_FS2 (1 << 15) @@ -193,10 +199,12 @@ int board_early_init_f(void) #endif /* Do any special system timer/TSC setup */ -#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) +#if IS_ENABLED(CONFIG_TEGRA_CLKRST) +# if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) if (!tegra_cpu_is_non_secure()) -#endif +# endif arch_timer_init(); +#endif pinmux_init(); board_init_uart_f(); From patchwork Thu Apr 4 11:59:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077187 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[217.229.27.37]) by smtp.gmail.com with ESMTPSA id l8sm20816211wrv.45.2019.04.04.04.59.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 04:59:50 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:26 +0200 Message-Id: <20190404115942.17947-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 03/19] ARM: tegra: Guard GP pad control code with a Kconfig symbol X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding The GP pad control code is not relevant on all Tegra SoC generations, so guard it with a Kconfig symbol that can be selected by the generations that need it. This is in preparation for unifying Tegra186 code with the code used on older generations. Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/Kconfig | 5 +++++ arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/cache.c | 2 ++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index ee078fec9adc..265051b18aaf 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -15,6 +15,9 @@ config SPL_SERIAL_SUPPORT config TEGRA_CLKRST bool +config TEGRA_GP_PADCTRL + bool + config TEGRA_IVC bool "Tegra IVC protocol" help @@ -61,6 +64,7 @@ config TEGRA_ARMV7_COMMON select TEGRA_CLKRST select TEGRA_COMMON select TEGRA_GPIO + select TEGRA_GP_PADCTRL select TEGRA_NO_BPMP config TEGRA_ARMV8_COMMON @@ -106,6 +110,7 @@ config TEGRA210 select TEGRA_ARMV8_COMMON select TEGRA_CLKRST select TEGRA_GPIO + select TEGRA_GP_PADCTRL select TEGRA_NO_BPMP config TEGRA186 diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 0e812818d7a2..69f802c01b45 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -13,7 +13,7 @@ else obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o endif -obj-y += ap.o +obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o obj-y += board.o board2.o obj-y += cache.o obj-$(CONFIG_TEGRA_CLKRST) += clock.o diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index be414e4e4aca..d7063490e222 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -8,7 +8,9 @@ #include #include #include +#if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL) #include +#endif #ifndef CONFIG_ARM64 void config_cache(void) From patchwork Thu Apr 4 11:59:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077188 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PcKVz9R8"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44ZhQd48Kvz9sPd for ; Thu, 4 Apr 2019 23:02:33 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 41073C21F01; Thu, 4 Apr 2019 12:01:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B0355C21E4E; Thu, 4 Apr 2019 11:59:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A88D3C21C29; Thu, 4 Apr 2019 11:59:56 +0000 (UTC) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by lists.denx.de (Postfix) with ESMTPS id CCCB3C21E34 for ; Thu, 4 Apr 2019 11:59:52 +0000 (UTC) Received: by mail-wm1-f68.google.com with SMTP id n25so3057338wmk.4 for ; Thu, 04 Apr 2019 04:59:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vIsy7p7abq4q3qRuBoqaZeKplgt8sPU+S2hipJa3ugQ=; b=PcKVz9R8cwrhVqOd8CCZUIoL3ytF0dBDJcqtw5u2fhsOiAmbJGYi34StgZWVS4W+eM XAw+Y2GOlyKDZw40GyKnQaRAJYTJZvMxv9QxPPiahLlGWMP94v4AyzLL5NtLQdbuIQJ+ PHkuAwPAfeLzmpvPA1C5865gO2yYutPzZEJSq/RzZqPfhoboYkmoQSBglcL4ZO71t7Py SOp9/Nx7JMVy7M7jGze6xr19iygDGNKxZg+5+B54GZMVbgqhryGmlC5CCF0rhM3hjmum SOPtv9b2tRyO6BALTJJd5+46iweU7aqCacCnoRVwLVKRy1Si9BUryAxiRTTSXI3kjajA VQtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vIsy7p7abq4q3qRuBoqaZeKplgt8sPU+S2hipJa3ugQ=; b=ZhCBNlU+Iij405xxAUcga3b8jUcPcX9eiNTD/j36CA+tsRffco+Kq4RTRar2qQmnfE 3eHYoc0s1ifwAPJPVXXmDTrOrMPHajfXksHo5E1SOmofuhIQH/POmJp5H19uFbw+mMLQ pRmiDSyhuYbkwvC5QPfyUhKN6rwQJ7WDLO6v4VvF+B/0f4B7hoVVU430MkanVt6KO0Sw F2A3Ox5L+DGYPe09sZvWcRn5IGZlMjuRSk89WrF+ZQ9vgwAwXKoKAItK2BvBcKCbhjBy bP3ZlRLxhSenVXrcDTM2qyl79BVlrnxUVNEJZvFOycxU7EMiUsApAsDaNc0WngLCsgBt EYJw== X-Gm-Message-State: APjAAAXrWfqqGoDet/oc3yZEW4nxYQwe6Kd4gR6fxK2WQP8WE585smAp FtgrKMDUNwyDw4uuxVkbMdc= X-Google-Smtp-Source: APXvYqxafv81DKzPZx2pV9m+G9jqeuUYBOdiuvZaW/nLUmpivQqbk6R4GGRjgexsiAYFg7OYIDyYLg== X-Received: by 2002:a7b:c403:: with SMTP id k3mr4017507wmi.58.1554379192417; Thu, 04 Apr 2019 04:59:52 -0700 (PDT) Received: from localhost (pD9E51B25.dip0.t-ipconnect.de. [217.229.27.37]) by smtp.gmail.com with ESMTPSA id h131sm3262488wmh.1.2019.04.04.04.59.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 04:59:51 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:27 +0200 Message-Id: <20190404115942.17947-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 04/19] ARM: tegra: Guard memory controller code with a Kconfig symbol X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Memory controller code is not relevant on all Tegra SoC generations, so guard it with a Kconfig symbol that can be selected by the generations that need it. This is in preparation for unifying Tegra186 code with the code used on older generations. Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/Kconfig | 5 +++++ arch/arm/mach-tegra/board.c | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 265051b18aaf..5763c4ae3cd1 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -26,6 +26,9 @@ config TEGRA_IVC U-Boot, it is typically used for communication between the main CPU and various auxiliary processors. +config TEGRA_MC + bool + config TEGRA_COMMON bool "Tegra common options" select BINMAN @@ -65,6 +68,7 @@ config TEGRA_ARMV7_COMMON select TEGRA_COMMON select TEGRA_GPIO select TEGRA_GP_PADCTRL + select TEGRA_MC select TEGRA_NO_BPMP config TEGRA_ARMV8_COMMON @@ -111,6 +115,7 @@ config TEGRA210 select TEGRA_CLKRST select TEGRA_GPIO select TEGRA_GP_PADCTRL + select TEGRA_MC select TEGRA_NO_BPMP config TEGRA186 diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index ecd5001de4c5..7ef5a67edd1f 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -13,7 +13,9 @@ #include #endif #include +#if IS_ENABLED(CONFIG_TEGRA_MC) #include +#endif #include #include #include @@ -68,6 +70,7 @@ bool tegra_cpu_is_non_secure(void) } #endif +#if IS_ENABLED(CONFIG_TEGRA_MC) /* Read the RAM size directly from the memory controller */ static phys_size_t query_sdram_size(void) { @@ -117,11 +120,15 @@ static phys_size_t query_sdram_size(void) return size_bytes; } +#endif int dram_init(void) { +#if IS_ENABLED(CONFIG_TEGRA_MC) /* We do not initialise DRAM here. We just query the size */ gd->ram_size = query_sdram_size(); +#endif + return 0; } From patchwork Thu Apr 4 11:59:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077207 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="qaSG1Bq/"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44ZhbK2W3Rz9sRV for ; Thu, 4 Apr 2019 23:10:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 74592C21E2B; Thu, 4 Apr 2019 12:04:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9896CC21E77; Thu, 4 Apr 2019 12:00:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 24892C21E12; Thu, 4 Apr 2019 11:59:57 +0000 (UTC) Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by lists.denx.de (Postfix) with ESMTPS id 5270DC21E39 for ; Thu, 4 Apr 2019 11:59:54 +0000 (UTC) Received: by mail-wr1-f68.google.com with SMTP id q1so3478539wrp.0 for ; Thu, 04 Apr 2019 04:59:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4xo4s8ctKfUMWm6yWCnpb6MvIeCW9frOdWam+8yu3bE=; b=qaSG1Bq/xbqd+un1+KyFTJx56c2WYj0fm4fHYtII+JFGffLhWdqRim4CbpsuU/WibU FvVBpPGYVQRdnlBNsSOSTX4irapEddxywFuKWHbGCs7fkd2JtkneZu27lOKNJ9vqi+FT JEJxUBqe3vHd85RQOq6B6JPD8TCctjhswlZz527OLU5uySZ/38PTTGFGLhRkVQ62Vagc cVFmmryHLvbRIo+ufJpOp6ZM9+GXrFsfu9LbGqHzBR0vmQ7ge3T0z1gFy1nHONlDZG7R BTxfqvkYGDK2NAI66QfvmGEYU25gkdCH4b7yLBTX1Pk0c/CZDF1Y4t1NMLtZ53saJQy6 eDCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4xo4s8ctKfUMWm6yWCnpb6MvIeCW9frOdWam+8yu3bE=; b=HUTUb6oFORWPXhFQ7ck2fiSpYZ9nurkfeWXHyW7SGynkrFTWtie+Z9EAR1nT0L/tXg G+GV/06TcGLqhCq/9zLQ9u+5VGGT6NP69qFHFYbpWbT7JAc2FF2P4qAewroKSwKOv/nC +emoKqieQdXgSlDFoyg5SN4bB5Z/zPz4uwWWknxCmH9MNeV5TLPNumKLFaIbL+eSGGBS NK6Mogu8ZBeNzbjQsOPIwhfBEmMMlPriEYRP0MkdtPONrQdtj2nGjjNv1j99Ke+llF6k 8qZXAL0jgEJmSprjh1QzvI5/I0e5cHVHeqRk4PwUwsB87VA7xKvSiUICxVdnZOcPYW5r VT7g== X-Gm-Message-State: APjAAAVjcWWdea5oGuF8+VVt/0japPOiwgFKLGZrwVsL8xJD7dEccAYM MreQysHoqSFD4W+BdrLnCjo= X-Google-Smtp-Source: APXvYqx8Bx+yLXA+t/UU95SNwXT3eHpfPq/SCMkB5xk0IW+gn++MuutImBzZlbwFkTKxWvbP1ROeFA== X-Received: by 2002:adf:b612:: with SMTP id f18mr3976346wre.236.1554379193908; Thu, 04 Apr 2019 04:59:53 -0700 (PDT) Received: from localhost (pD9E51B25.dip0.t-ipconnect.de. [217.229.27.37]) by smtp.gmail.com with ESMTPSA id y127sm19055221wmg.29.2019.04.04.04.59.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 04:59:53 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:28 +0200 Message-Id: <20190404115942.17947-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 05/19] ARM: tegra: Guard pin controller code with a Kconfig symbol X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Pin controller code is not relevant on all Tegra SoC generations, so guard it with a Kconfig symbol that can be selected by the generations that need it. This is in preparation for unifying Tegra186 code with the code used on older generations. Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/Kconfig | 5 +++++ arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/board.c | 6 ++++++ arch/arm/mach-tegra/board2.c | 2 ++ 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 5763c4ae3cd1..be20ac2e804e 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -29,6 +29,9 @@ config TEGRA_IVC config TEGRA_MC bool +config TEGRA_PINCTRL + bool + config TEGRA_COMMON bool "Tegra common options" select BINMAN @@ -70,6 +73,7 @@ config TEGRA_ARMV7_COMMON select TEGRA_GP_PADCTRL select TEGRA_MC select TEGRA_NO_BPMP + select TEGRA_PINCTRL config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" @@ -117,6 +121,7 @@ config TEGRA210 select TEGRA_GP_PADCTRL select TEGRA_MC select TEGRA_NO_BPMP + select TEGRA_PINCTRL config TEGRA186 bool "Tegra186 family" diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 69f802c01b45..395e0191a458 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -17,7 +17,7 @@ obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o obj-y += board.o board2.o obj-y += cache.o obj-$(CONFIG_TEGRA_CLKRST) += clock.o -obj-y += pinmux-common.o +obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o obj-y += powergate.o obj-y += xusb-padctl-dummy.o endif diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 7ef5a67edd1f..b65bdde5a78d 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -12,7 +12,9 @@ #if IS_ENABLED(CONFIG_TEGRA_CLKRST) #include #endif +#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) #include +#endif #if IS_ENABLED(CONFIG_TEGRA_MC) #include #endif @@ -132,6 +134,7 @@ int dram_init(void) return 0; } +#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) static int uart_configs[] = { #if defined(CONFIG_TEGRA20) #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) @@ -199,9 +202,11 @@ static void setup_uarts(int uart_ids) } } } +#endif void board_init_uart_f(void) { +#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) int uart_ids = 0; /* bit mask of which UART ids to enable */ #ifdef CONFIG_TEGRA_ENABLE_UARTA @@ -220,6 +225,7 @@ void board_init_uart_f(void) uart_ids |= UARTE; #endif setup_uarts(uart_ids); +#endif } #if !CONFIG_IS_ENABLED(OF_CONTROL) diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index b94077221f77..ce1c9346959d 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -25,8 +25,10 @@ #if IS_ENABLED(CONFIG_TEGRA_CLKRST) #include #endif +#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) #include #include +#endif #include #ifdef CONFIG_TEGRA_CLOCK_SCALING #include From patchwork Thu Apr 4 11:59:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077193 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[217.229.27.37]) by smtp.gmail.com with ESMTPSA id m6sm27265178wrr.53.2019.04.04.04.59.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 04:59:54 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:29 +0200 Message-Id: <20190404115942.17947-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 06/19] ARM: tegra: Guard powergate code with a Kconfig symbol X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Powergate code is not relevant on all Tegra SoC generations, so guard it with a Kconfig symbol that can be selected by the generations that need it. This is in preparation for unifying Tegra186 code with the code used on older generations. Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/Kconfig | 5 +++++ arch/arm/mach-tegra/Makefile | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index be20ac2e804e..db9198348d3f 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -32,6 +32,9 @@ config TEGRA_MC config TEGRA_PINCTRL bool +config TEGRA_PMC + bool + config TEGRA_COMMON bool "Tegra common options" select BINMAN @@ -74,6 +77,7 @@ config TEGRA_ARMV7_COMMON select TEGRA_MC select TEGRA_NO_BPMP select TEGRA_PINCTRL + select TEGRA_PMC config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" @@ -122,6 +126,7 @@ config TEGRA210 select TEGRA_MC select TEGRA_NO_BPMP select TEGRA_PINCTRL + select TEGRA_PMC config TEGRA186 bool "Tegra186 family" diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 395e0191a458..517be21ee5f5 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -18,7 +18,7 @@ obj-y += board.o board2.o obj-y += cache.o obj-$(CONFIG_TEGRA_CLKRST) += clock.o obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o -obj-y += powergate.o +obj-$(CONFIG_TEGRA_PMC) += powergate.o obj-y += xusb-padctl-dummy.o endif From patchwork Thu Apr 4 11:59:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077195 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="G/PnSK8U"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44ZhVD2PF7z9sPd for ; Thu, 4 Apr 2019 23:05:40 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0BCA7C21E52; Thu, 4 Apr 2019 12:04:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3188FC21E8A; Thu, 4 Apr 2019 12:00:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C809FC21E3A; Thu, 4 Apr 2019 12:00:00 +0000 (UTC) Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by lists.denx.de (Postfix) with ESMTPS id 1D7E5C21E1B for ; Thu, 4 Apr 2019 11:59:57 +0000 (UTC) Received: by mail-wm1-f67.google.com with SMTP id h18so3073303wml.1 for ; Thu, 04 Apr 2019 04:59:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0lXOOQuXI1boLHkBibzrwwKkGSC4FIeMQ4YHpx1emgo=; b=G/PnSK8Uc1EXtflp4zcxbOb7l6FDUDMCnuk7apjDaCiVbFzQ+joJS5zs+T4H/NZRBt /zruQ+55iOUbxY1OxZd5tRfSeAy47eGpxzvjBNjjUSNXJ8nh1eZ8n/+YIarhV60V9rLy pkow8GH4JNlzyPXVU1c2yc7dj5Dc00wiN+zSRu4Grc8ag4hmmX24e5Y8KJIQiVxTlMjA +Rr/DedV4OCsHXQ9rzo68IPCuBTQWmESLGcBe43kNDYmJXabUXuJ0i8FUjtAb/Cw9xcT CJAr7IryPetSuzL38ELbyMdVnld2j/gJLMW5HzOtNCny6R9Fl5T8k8fdg3eVlKrv2gZc b1SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0lXOOQuXI1boLHkBibzrwwKkGSC4FIeMQ4YHpx1emgo=; b=QhL15LTPzdgCCkbp0S8WaTAtjitqujv7GuweRDofnyqAV1VkjT/61//P/8iTe55N23 ZEwsdo1xJ0fpyhtA0fEXOmWr4/yX2yG9utts1+ASIPMxwGgQkNKM7TysyJXK9SeBxpaC EUikCkvMmNxE8Ynh9RQVuGDmJtCh4yVNzVs9VC3uoIkD6yFXQZV93++DAQneLRhPB4Fh F3BBWAjRxAoaRm2hQgzzXdRRoQI84PFmVkMPojUZ7SJMKczKprrQlxYCyYlfJFt7Q8u2 e4Th1d6DFBAhFLoLqAdlJTm89kR7O6f0kXqRwM7Z8YeLP2NmNndHNl8RUeJEtaK4S8Jg kZJg== X-Gm-Message-State: APjAAAVfq2OTSCAH+Thz5c1zRdU4Gf2QZvt3ZnIBWyDz3faIkOLA9dAp fTnI7S0FnXtXs91YGpU+D/0= X-Google-Smtp-Source: APXvYqzq0wHyt32qrlY6L1pD4Isl4MQvSzu+FaLINZQGkH6JAscdWeEPAEFAZ/SnlXJQUIrUzLT/fg== X-Received: by 2002:a1c:7e0e:: with SMTP id z14mr3676747wmc.95.1554379196715; Thu, 04 Apr 2019 04:59:56 -0700 (PDT) Received: from localhost (pD9E51B25.dip0.t-ipconnect.de. [217.229.27.37]) by smtp.gmail.com with ESMTPSA id v16sm35069517wro.48.2019.04.04.04.59.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 04:59:56 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:30 +0200 Message-Id: <20190404115942.17947-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 07/19] ARM: tegra: Fix save_boot_params() prototype X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding The save_boot_params() function takes as its first four arguments the first four registers. On 32-bit ARM these are r0, r1, r2 and r3, all of which are 32 bits wide. However, on 64-bit ARM thene registers are x0, x1, x2 and x3, all of which are 64 bits wide. In order to allow reusing the save_boot_params() implementation on 64-bit ARM, change it to take unsigned long parameters rather than the fixed size 32-bit integers. This ensures that the correct values are passed. Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/board.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index b65bdde5a78d..59d2f347485d 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -42,7 +42,8 @@ enum { static bool from_spl __attribute__ ((section(".data"))); #ifndef CONFIG_SPL_BUILD -void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) { from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; save_boot_params_ret(); From patchwork Thu Apr 4 11:59:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077192 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="qpmVms+H"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44ZhSd1TJbz9sPd for ; Thu, 4 Apr 2019 23:04:17 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D50C0C21C38; Thu, 4 Apr 2019 12:04:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 119F1C21E26; Thu, 4 Apr 2019 12:00:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9443BC21E89; Thu, 4 Apr 2019 12:00:02 +0000 (UTC) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by lists.denx.de (Postfix) with ESMTPS id 7F703C21E34 for ; Thu, 4 Apr 2019 11:59:58 +0000 (UTC) Received: by mail-wm1-f65.google.com with SMTP id z6so7158723wmi.0 for ; Thu, 04 Apr 2019 04:59:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aTP9o+VrfeJyMgz+/n+XrpA/YtWhzuJxsjzFB2LbsEM=; b=qpmVms+HbuskV4YNzx1eTQcppq4gnUzNEu1/TfIiQyHnEf1enEZJjt51+rxeLwECTV 3yAhayYuQi7xLZ2WCgLbHoPMV4k2IGmGgmkQgpybkjjqsp7hNtKCbCFmJrWO2wCrD0FN DzqHdTv8zhJWdUjDsj8yxOIMX2J01ymZCJ/XP9QXVeNXf8m9ycde5pWYIOGeZ7w5S/sr kePhUzx+CdUXXo/3rtV4uGi2UV8h+wUeHllL3Dc8McZoSfjAVa+4Mi8KEDxgFfnUU4DJ s+XodyGdBMPLkSiQfG00xpGh9fqDg5mKSHVOCTwyXO85jhrEgF9Ho7nsmTvETm+g6zRp qSZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aTP9o+VrfeJyMgz+/n+XrpA/YtWhzuJxsjzFB2LbsEM=; b=fK9VQeQN3PXPGfzJ5uflzmr01Ns8n8/N4j6mtep1gdTtDnAW5PblskG7Rmz2UQbvZH H2qLySw9iIVRVZVrs1QGg4MS9RCVQDBR/HxUyBw+ApqTffVIgin4lx3wOjOAenHJz/Ao pxKpb+b8n2fRuaYNeWn5xw3rEBtDYzzbKHcrrppdMzfBvEkwtiR5PFPjPLvjg4OvlBxV HZhBfcZAHiit4bvp8ltlsvb7qkrsSDm9+wkfm3NuRBIltypMm+n1TsNxSkNuDBxrH5Bl yyeuNaLS9zGprmQAYz0BmtReEnrVOCFeeNes1+CtdupISipGSllP+EZvB5zuZ5M240tJ +Hzw== X-Gm-Message-State: APjAAAVwrGgMEDb9E/fgUW2CWApZBLntZV9n/FvIXxrAsxQwFSSQxqSx o+MvCmnGcFqSzVBG1i2Tt+k= X-Google-Smtp-Source: APXvYqz6RNWmwQl/zLml3n3rOd+qhZ+L6RFHR81JdhWgIfAIjWqHiAaXL3ziMfgMGaKG63Y19tLkJw== X-Received: by 2002:a1c:e70b:: with SMTP id e11mr3657109wmh.17.1554379198073; Thu, 04 Apr 2019 04:59:58 -0700 (PDT) Received: from localhost (pD9E51B25.dip0.t-ipconnect.de. [217.229.27.37]) by smtp.gmail.com with ESMTPSA id c16sm17290998wme.31.2019.04.04.04.59.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 04:59:57 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:31 +0200 Message-Id: <20190404115942.17947-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 08/19] ARM: tegra: Allow boards to override boot target devices X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Boards may not support all the boot target devices in the default list for Tegra devices. Allow a board to override the list and default to the standard list only if the board hasn't specified one itself. Signed-off-by: Thierry Reding --- include/configs/tegra-common-post.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index e54428ba43e2..9685ee5059ab 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -21,12 +21,14 @@ #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ #ifndef CONFIG_SPL_BUILD +#ifndef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) +#endif #include #else #define BOOTENV From patchwork Thu Apr 4 11:59:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077197 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="rIJgftuG"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44ZhX96FRSz9sPn for ; Thu, 4 Apr 2019 23:07:20 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8C14EC21E26; Thu, 4 Apr 2019 12:04:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B263CC21E74; Thu, 4 Apr 2019 12:00:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 03D59C21C3F; Thu, 4 Apr 2019 12:00:03 +0000 (UTC) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by lists.denx.de (Postfix) with ESMTPS id 027EDC21E53 for ; Thu, 4 Apr 2019 12:00:00 +0000 (UTC) Received: by mail-wm1-f66.google.com with SMTP id w15so3066483wmc.3 for ; Thu, 04 Apr 2019 05:00:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5b0o0vW3ad+YZN7OTN68zmmqfo7lLldUCm2C7C3RI60=; b=rIJgftuGjCFXqW1VDiOpvuMOe1xj016TU5iUri1xMEVHJ2n/xpJseCbGK2zvOi/0aY AvnYnb5C8Ha7NrGAD+EzXuAes91ApbPUzyA6FUBmP4aQ8Zh4shndyfhmQt6lPmFVIwTC +F12WT1Jonc0WkEPwb4tvOQQwe1CXEv+nU1IR8OF8+opT/c7w5ooD707ECG37S9JhV1R 8Mh9dG/8EKjmaB7LBCXUaTwi6NE/dNomns2N2y3znHPx/vOr8AW8BljaATpo+fk7voF0 HN1Ul7s0LvpBwbtM/GPK3/XuV3XioR6S/2LqQXv0Xvqhjc3LDGmBjAETOo7lVeNqg/EP F13g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5b0o0vW3ad+YZN7OTN68zmmqfo7lLldUCm2C7C3RI60=; b=ffSikW0rYpfGgEsLS++3almDYKEHMTFhRlSNTKulDQOYxa2tq+TL+9f6TU5BX4e8vv NzIyCu+E7+ZNjH2Ltr4B2jEEhtqGjlPfhJoKJpJBvA2U8Ue3AfRF0hYxKw+J5tPP+R6t 29r+yHoTXSOOOAThazKytpveGanCr7lujpO8RkAaSKDU7elmSUGHL7pfmWq5knIerT7R fOWM1rTx+NW0mOvqS3BZt36EyUfwS8ahidtE9JPuIfhBbbPq7ACNWondc+8gAwKNWNCq /dTi9s7QAkpGtt2O38hbGRajXbgigzszYPOKSlz1bN5+ybmJRhls376f/7Ag4B4wfj9t 8Icg== X-Gm-Message-State: APjAAAUeFKvuZ+zFf82zLxn+g9fez848sSSoKR679m87BWvX3SNHbN6R LgvPqKPjbhF0pNudlLpVBQQ= X-Google-Smtp-Source: APXvYqyA5wwV5OfLoDeMoa+ruOiJmVZglC2O/msoQXMYTFIV4ujcMJXWX1rN5gKa0kRXSxWe821Gkw== X-Received: by 2002:a1c:6c04:: with SMTP id h4mr3864523wmc.135.1554379199461; Thu, 04 Apr 2019 04:59:59 -0700 (PDT) Received: from localhost (pD9E51B25.dip0.t-ipconnect.de. [217.229.27.37]) by smtp.gmail.com with ESMTPSA id z1sm16438385wrs.52.2019.04.04.04.59.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 04:59:58 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:32 +0200 Message-Id: <20190404115942.17947-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 09/19] ARM: tegra: Support TZ-only access to PMC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Some devices may restrict access to the PMC to TrustZone software only. Non-TZ software can detect this and use SMC calls to the firmware that runs in the TrustZone to perform accesses to PMC registers. Note that this also fixes reset_cpu() and the enterrcm command on Tegra186 where they were previously trying to access the PMC at a wrong physical address. Based on work by Kalyani Chidambaram and Tom Warren . Signed-off-by: Thierry Reding --- arch/arm/include/asm/arch-tegra/pmc.h | 20 +++++- arch/arm/include/asm/arch-tegra/tegra.h | 6 ++ arch/arm/mach-tegra/Kconfig | 5 ++ arch/arm/mach-tegra/Makefile | 4 +- arch/arm/mach-tegra/clock.c | 13 ++-- arch/arm/mach-tegra/cmd_enterrcm.c | 6 +- arch/arm/mach-tegra/cpu.c | 20 +++--- arch/arm/mach-tegra/lowlevel_init.S | 39 ----------- arch/arm/mach-tegra/pmc.c | 92 +++++++++++++++++++++++++ arch/arm/mach-tegra/powergate.c | 11 +-- 10 files changed, 151 insertions(+), 65 deletions(-) delete mode 100644 arch/arm/mach-tegra/lowlevel_init.S create mode 100644 arch/arm/mach-tegra/pmc.c diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h index 34bbe75d5fdb..1524bf291164 100644 --- a/arch/arm/include/asm/arch-tegra/pmc.h +++ b/arch/arm/include/asm/arch-tegra/pmc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2019 * NVIDIA Corporation */ @@ -388,4 +388,22 @@ struct pmc_ctlr { /* APBDEV_PMC_CNTRL2_0 0x440 */ #define HOLD_CKE_LOW_EN (1 << 12) +/* PMC read/write functions */ +u32 tegra_pmc_readl(unsigned long offset); +void tegra_pmc_writel(u32 value, unsigned long offset); + +#define PMC_CNTRL 0x0 +#define PMC_CNTRL_MAIN_RST BIT(4) + +#if IS_ENABLED(CONFIG_TEGRA186) +# define PMC_SCRATCH0 0x32000 +#else +# define PMC_SCRATCH0 0x00050 +#endif + +/* for secure PMC */ +#define TEGRA_SMC_PMC 0xc2fffe00 +#define TEGRA_SMC_PMC_READ 0xaa +#define TEGRA_SMC_PMC_WRITE 0xbb + #endif /* PMC_H */ diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 7ae0129e2db3..7a4e0972fb76 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -30,7 +30,13 @@ #define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) #define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) #define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ + defined(CONFIG_TEGRA114) || defined(CONFIG_TEGRA124) || \ + defined(CONFIG_TEGRA132) || defined(CONFIG_TEGRA210) #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) +#else +#define NV_PA_PMC_BASE 0xc360000 +#endif #define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index db9198348d3f..28914a34a1b5 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -35,6 +35,10 @@ config TEGRA_PINCTRL config TEGRA_PMC bool +config TEGRA_PMC_SECURE + bool + depends on TEGRA_PMC + config TEGRA_COMMON bool "Tegra common options" select BINMAN @@ -127,6 +131,7 @@ config TEGRA210 select TEGRA_NO_BPMP select TEGRA_PINCTRL select TEGRA_PMC + select TEGRA_PMC_SECURE config TEGRA186 bool "Tegra186 family" diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 517be21ee5f5..f8bc65aa8b18 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# (C) Copyright 2010-2015 Nvidia Corporation. +# (C) Copyright 2010-2019 Nvidia Corporation. # # (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -27,11 +27,11 @@ obj-y += dt-setup.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_GPU) += gpu.o obj-$(CONFIG_TEGRA_IVC) += ivc.o -obj-y += lowlevel_init.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o endif obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o +obj-y += pmc.o obj-$(CONFIG_TEGRA20) += tegra20/ obj-$(CONFIG_TEGRA30) += tegra30/ diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 096330748f2b..c9cd4e6aaeb7 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved. */ /* Tegra SoC common clock control functions */ @@ -814,11 +814,16 @@ void tegra30_set_up_pllp(void) int clock_external_output(int clk_id) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 val; if (clk_id >= 1 && clk_id <= 3) { - setbits_le32(&pmc->pmc_clk_out_cntrl, - 1 << (2 + (clk_id - 1) * 8)); + val = tegra_pmc_readl(offsetof(struct pmc_ctlr, + pmc_clk_out_cntrl)); + val |= 1 << (2 + (clk_id - 1) * 8); + tegra_pmc_writel(val, + offsetof(struct pmc_ctlr, + pmc_clk_out_cntrl)); + } else { printf("%s: Unknown output clock id %d\n", __func__, clk_id); return -EINVAL; diff --git a/arch/arm/mach-tegra/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c index 4e6beb3e5bb4..4a889f0e3422 100644 --- a/arch/arm/mach-tegra/cmd_enterrcm.c +++ b/arch/arm/mach-tegra/cmd_enterrcm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved. * * Derived from code (arch/arm/lib/reset.c) that is: * @@ -31,12 +31,10 @@ static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - puts("Entering RCM...\n"); udelay(50000); - pmc->pmc_scratch0 = 2; + tegra_pmc_writel(2, PMC_SCRATCH0); disable_interrupts(); reset_cpu(0); diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index 1b6ad074ed8f..3d140760e68f 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved. */ #include @@ -299,21 +299,19 @@ void enable_cpu_clock(int enable) static int is_cpu_powered(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - - return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; + return (tegra_pmc_readl(offsetof(struct pmc_ctlr, + pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0; } static void remove_cpu_io_clamps(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; debug("%s entry\n", __func__); /* Remove the clamps on the CPU I/O signals */ - reg = readl(&pmc->pmc_remove_clamping); + reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping)); reg |= CPU_CLMP; - writel(reg, &pmc->pmc_remove_clamping); + tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping)); /* Give I/O signals time to stabilize */ udelay(IO_STABILIZATION_DELAY); @@ -321,17 +319,19 @@ static void remove_cpu_io_clamps(void) void powerup_cpu(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; int timeout = IO_STABILIZATION_DELAY; debug("%s entry\n", __func__); if (!is_cpu_powered()) { /* Toggle the CPU power state (OFF -> ON) */ - reg = readl(&pmc->pmc_pwrgate_toggle); + reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, + pmc_pwrgate_toggle)); reg &= PARTID_CP; reg |= START_CP; - writel(reg, &pmc->pmc_pwrgate_toggle); + tegra_pmc_writel(reg, + offsetof(struct pmc_ctlr, + pmc_pwrgate_toggle)); /* Wait for the power to come up */ while (!is_cpu_powered()) { diff --git a/arch/arm/mach-tegra/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S deleted file mode 100644 index 626f1b642745..000000000000 --- a/arch/arm/mach-tegra/lowlevel_init.S +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SoC-specific setup info - * - * (C) Copyright 2010,2011 - * NVIDIA Corporation - */ - -#include -#include - -#ifdef CONFIG_ARM64 - .align 5 -ENTRY(reset_cpu) - /* get address for global reset register */ - ldr x1, =PRM_RSTCTRL - ldr w3, [x1] - /* force reset */ - orr w3, w3, #0x10 - str w3, [x1] - mov w0, w0 -1: - b 1b -ENDPROC(reset_cpu) -#else - .align 5 -ENTRY(reset_cpu) - ldr r1, rstctl @ get addr for global reset - @ reg - ldr r3, [r1] - orr r3, r3, #0x10 - str r3, [r1] @ force reset - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PRM_RSTCTRL -ENDPROC(reset_cpu) -#endif diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c new file mode 100644 index 000000000000..afd3c54179c1 --- /dev/null +++ b/arch/arm/mach-tegra/pmc.c @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + */ + +#include + +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE) +static bool tegra_pmc_detect_tz_only(void) +{ + static bool initialized = false; + static bool is_tz_only = false; + u32 value, saved; + + if (!initialized) { + saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0); + value = saved ^ 0xffffffff; + + if (value == 0xffffffff) + value = 0xdeadbeef; + + /* write pattern and read it back */ + writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0); + value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0); + + /* if we read all-zeroes, access is restricted to TZ only */ + if (value == 0) { + debug("access to PMC is restricted to TZ\n"); + is_tz_only = true; + } else { + /* restore original value */ + writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0); + } + + initialized = true; + } + + return is_tz_only; +} +#endif + +uint32_t tegra_pmc_readl(unsigned long offset) +{ +#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE) + if (tegra_pmc_detect_tz_only()) { + struct arm_smccc_res res; + + arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, + 0, 0, 0, &res); + if (res.a0) + printf("%s(): SMC failed: %lu\n", __func__, res.a0); + + return res.a1; + } +#endif + + return readl(NV_PA_PMC_BASE + offset); +} + +void tegra_pmc_writel(u32 value, unsigned long offset) +{ +#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE) + if (tegra_pmc_detect_tz_only()) { + struct arm_smccc_res res; + + arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, + value, 0, 0, 0, 0, &res); + if (res.a0) + printf("%s(): SMC failed: %lu\n", __func__, res.a0); + + return; + } +#endif + + writel(value, NV_PA_PMC_BASE + offset); +} + +void reset_cpu(ulong addr) +{ + u32 value; + + value = tegra_pmc_readl(PMC_CNTRL); + value |= PMC_CNTRL_MAIN_RST; + tegra_pmc_writel(value, PMC_CNTRL); +} diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index e45f0961b242..761c9ef19e3b 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. */ #include @@ -11,6 +11,7 @@ #include #include +#include #define PWRGATE_TOGGLE 0x30 #define PWRGATE_TOGGLE_START (1 << 8) @@ -24,18 +25,18 @@ static int tegra_powergate_set(enum tegra_powergate id, bool state) u32 value, mask = state ? (1 << id) : 0, old_mask; unsigned long start, timeout = 25; - value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); + value = tegra_pmc_readl(PWRGATE_STATUS); old_mask = value & (1 << id); if (mask == old_mask) return 0; - writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE); + tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); start = get_timer(0); while (get_timer(start) < timeout) { - value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); + value = tegra_pmc_readl(PWRGATE_STATUS); if ((value & (1 << id)) == mask) return 0; } @@ -69,7 +70,7 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id) else value = 1 << id; - writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING); + tegra_pmc_writel(value, REMOVE_CLAMPING); return 0; } From patchwork Thu Apr 4 11:59:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077191 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hYWXVW25"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44ZhRw0HsNz9sPd for ; Thu, 4 Apr 2019 23:03:39 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A483FC21E4E; Thu, 4 Apr 2019 12:03:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 25F3FC21DE8; Thu, 4 Apr 2019 12:00:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C3519C21E34; Thu, 4 Apr 2019 12:00:04 +0000 (UTC) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by lists.denx.de (Postfix) with ESMTPS id 58EB8C21E62 for ; Thu, 4 Apr 2019 12:00:01 +0000 (UTC) Received: by mail-wm1-f66.google.com with SMTP id q16so2715734wmj.3 for ; Thu, 04 Apr 2019 05:00:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kTCp9zuL8j0HXOwn+YYh9d9LqP7nQOqkSB6WZHcITFU=; b=hYWXVW25vzjZndTMrLubXWSU02WGcZ5JBVjjsOHJ3ZPoX6TIbFtTDLnlvG76PumOXG msRINBnWw1eGHnzyodqklWNJ4R60E9onVi5sPj3gkzIHHU4aItStLWh2N2VZwB5haMR0 y+svpPipiMrL0aiMTnWCpIhSOrq8gaDbETiAhXi8Vxfeem30rvpViD0R4XcigMzoGUat ajRGnJSS8wNkQByZo00sAPc+ITUqbpnuvmCbDozFhUEd6eKM04vPZZb8POGcvSwkkuXq z3WNnpIO1buhaf6RBTwPaUuDwK5ox7SfhHDuWfqxQZKWFQjISeemSzvIQp5nV/jAc8YM lJ7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kTCp9zuL8j0HXOwn+YYh9d9LqP7nQOqkSB6WZHcITFU=; b=arFCBugGFKyBSoLh/ilZ9xO+Txd8Lhy+VgjhRsxCCzjCctsakxXEpikWRqWMavw38X ob3XpOgSManbiMe25dC/TRQRW5vcDown9JD8zkDUV7+JfvMbr+4ZSERaUKVCwKsr02/m pGDfoqRVh1ZwetMVRkJAajYKUnxLKbvJFq6llpbSzSwPFvmQ6U3nxgyfZPK1VdzJt5GU G24Vecne/doWqQL+gakaDW89Ty/NqG+sOPzi3jmAzQDVQl3ORURCr2QQTQP3J89/UQVt +UO6zK+iVC6tnS4lfu8OVIlvFMl8HkuysjJQGqlY1PopH6VIyhlaQHddU9JG+/xfnBbY QOKg== X-Gm-Message-State: APjAAAUXR31fNbAqCStKbosjeNg6Fvb6v9jXhUoQ1vRq8KFi5lddSkQF oLLuYkmIThLDUdKsW1StX4XiZT1D X-Google-Smtp-Source: APXvYqyqJGDrmXfEoAY0XBXepDA9ozH3k80pBw2uQLfm2M/dU9WcgRhlNf4NVt33wviynHYn2jk2Cg== X-Received: by 2002:a1c:a711:: with SMTP id q17mr3829057wme.111.1554379200926; Thu, 04 Apr 2019 05:00:00 -0700 (PDT) Received: from localhost (pD9E51B25.dip0.t-ipconnect.de. [217.229.27.37]) by smtp.gmail.com with ESMTPSA id z23sm9191883wma.0.2019.04.04.05.00.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 05:00:00 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:33 +0200 Message-Id: <20190404115942.17947-11-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 10/19] ARM: tegra: Workaround UDC boot issues only if necessary X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Resetting the USB device controller on boot is only necessary if the SoC actually has a UDC controller and U-Boot enables support for it. All the Tegra boards support UDC via the ChipIdea UDC driver, so make the UDC on boot workaround depend on the ChipIdea UDC driver. This prevents a crash on Tegra186 which does not have the ChipIdea UDC. Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 28914a34a1b5..faa73559fd42 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -148,6 +148,7 @@ endchoice config TEGRA_DISCONNECT_UDC_ON_BOOT bool "Disconnect USB device mode controller on boot" + depends on CI_UDC default y help When loading U-Boot into RAM over USB protocols using tools such as From patchwork Thu Apr 4 11:59:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077194 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Fchfe3EE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44ZhV40jpZz9sPf for ; Thu, 4 Apr 2019 23:05:32 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BEF21C21E1D; Thu, 4 Apr 2019 12:05:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 524B2C21E0D; Thu, 4 Apr 2019 12:00:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F1EAAC21E6A; Thu, 4 Apr 2019 12:00:07 +0000 (UTC) Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by lists.denx.de (Postfix) with ESMTPS id C2200C21E39 for ; Thu, 4 Apr 2019 12:00:02 +0000 (UTC) Received: by mail-wr1-f48.google.com with SMTP id y7so3389729wrn.11 for ; Thu, 04 Apr 2019 05:00:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vUCRGb7AncIDRmTICK080QFNWJmjPE6DuxvQYmiQGfs=; b=Fchfe3EE5mUaAWiDg5AoWg2BOz3WnKFHioHJ+TV4Pu1mrY88sg84FuBfVgsiQm3cSs z2QmTvsAPKUbrA5xXaovMd471y1xCb0Q6CGs0j+qQgYexmDjY4Bgg33p4NuROqmt3AxF z/FCVBGwpRW5W9kEe8LS7wSnci6ogfaaFQrUs04XYbGQl5Ni2CXQCwvCeefSSjfqgSCG 8aKDdQ/NtdUF5F2F5fvfQbxQHj1Ctdp7VOzUs24SjfQy5m+XaotjPiAjiug5RaYgwkkc GuzcfnobNs6RNkAZJxRiKvWtRDJ0zX7PQzHBwFukPwX/RwyTO/i1cCebzXux3+vKOGgG 6jug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vUCRGb7AncIDRmTICK080QFNWJmjPE6DuxvQYmiQGfs=; b=gjkYUu3T3TjV5lUDzbAT7Spu7PjsjnaMJggKovRoW43B6wDq/rjFkCrLyb3ZjdlM/A OyTRuN3J/dcckTaoZ4EB3PwxbCRouaVZets0JxftmEz2jH4HgsnBbuWGBDOPeZQQtZ6u I4MHcjrOgF5d4rBHZ67OJeGIvIwYIv2itEZW6BEbdChvw1HdC+QQnONp4mncX7FKylMF RMt8IqLPRk2lB9VAbF7F1UIOpcuuijGXdUlb9lBrUgXatE0zlSWrtPVNVcXGumgahXXC 2hd7RJ8JIplumtGKoEybvLkxMcpeG8mJkYtc+zxkBmVqFh62WSZcICVAiulzHCi2qBFz uPjw== X-Gm-Message-State: APjAAAUEhXfEdpodczrLMhcD8i2n1pxAZOaqDpnE7F+A35IyDyWT2Ykt rUjNeAUWV/zbdiwbeDjyfEE2VQCu X-Google-Smtp-Source: APXvYqyUTm0/LLj4zUMyEGxccolmVkyXeTxPUdX9HSfKSNI+c0+LfDHFqJO8MezedjUi35I734Bksw== X-Received: by 2002:adf:c60e:: with SMTP id n14mr3917427wrg.127.1554379202384; Thu, 04 Apr 2019 05:00:02 -0700 (PDT) Received: from localhost (pD9E51B25.dip0.t-ipconnect.de. [217.229.27.37]) by smtp.gmail.com with ESMTPSA id a187sm2076665wma.32.2019.04.04.05.00.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 05:00:01 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:34 +0200 Message-Id: <20190404115942.17947-12-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 11/19] ARM: tegra: Restore DRAM bank count X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") reduced the number of DRAM banks supported by U-Boot from 1026 to 8 on P2771-000 boards. However, as explained in commit a9819b9e33bd ("ARM: tegra: p2771-000: increase max DRAM bank count"), the platform can have a large number of unusable chunks of memory (up to 1024), so a total of 1026 DRAM banks are needed to describe the worst-case situation. In practice the number of DRAM banks needed will typically be much lower, but we should be prepared to properly deal with the worst case. Signed-off-by: Thierry Reding --- configs/p2771-0000-000_defconfig | 2 +- configs/p2771-0000-500_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index ac85efa37b3b..ad0802067e73 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_TEGRA186=y -CONFIG_NR_DRAM_BANKS=8 +CONFIG_NR_DRAM_BANKS=1026 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index df4d914d85cf..459b67fd195f 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_TEGRA186=y -CONFIG_NR_DRAM_BANKS=8 +CONFIG_NR_DRAM_BANKS=1026 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y From patchwork Thu Apr 4 11:59:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077204 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="GZyBy8+3"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44ZhYP23S6z9sPf for ; Thu, 4 Apr 2019 23:08:24 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 792CCC21DE8; Thu, 4 Apr 2019 12:05:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 22C10C21E38; Thu, 4 Apr 2019 12:00:26 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 232E4C21E6A; Thu, 4 Apr 2019 12:00:15 +0000 (UTC) Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by lists.denx.de (Postfix) with ESMTPS id BC820C21E1E for ; Thu, 4 Apr 2019 12:00:04 +0000 (UTC) Received: by mail-wr1-f49.google.com with SMTP id y7so3389898wrn.11 for ; Thu, 04 Apr 2019 05:00:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PlKbyzlPfaGGiqORC8Plmoh66R+p8wpSevr4CHFNYJQ=; b=GZyBy8+3C+NGowC+1KIn6WyZd0VNz5sl41gG6wJIZTzMUt13pmxqUlS1sO94P04dOu FksT1KIuG4VERRS4aLuchZ6zoRnRy8L+RDipKxxc/CYfduHwuxXX8CA3heKse7tDPUQh dIu5xEnJXpRYp6ahaNQWVpCUY++VwqGIMh0Qaoz8KuJngG1S9qCJ7mrcIMFNaxWjfoLH yhVs49JjCjCudviDxOsU4l764udCCMkU6j2ggciXul5RIthJRjWbS/aXiHQ/U+yD7Yx2 xPM1ggLtwqKqqyyx9EDgVhyWC8cX2mMqNzmLhTL+p/dR+qtaV+K872etIaktfAwZZEdo tbag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PlKbyzlPfaGGiqORC8Plmoh66R+p8wpSevr4CHFNYJQ=; b=pRF4QJHZHT1r5C0fADBFa9NrTz32mPVxdJhVlYNpvUh7/nvaSAp2R5UByZ4v4cReQJ 5OrMjbuzI8cROWXo91Uu/6JTmG1MZlATuKcmlEAFyWKBHKXt4VBmXuq/49TKhqKzjzSB yt4b7q+sglTrVgF6XJi8ZtWI0foKO1hlrfI13opFrYvqAdgzHnDGYG44hB6RQcagXHNX HsDTQYqpMDulss5g0LA9sf7xyrpoSkKcgot4NxYX9TJaqtg8DvEqlopQ+/KhTg+cSssg 8cRLnpgkh1i+lmUpxnMVyUw76sN+5+a9oehFQVlFP9FYWtnf09HgfFUj/UOfEMu+mPqq fBhA== X-Gm-Message-State: APjAAAV8eGZE76M6W56KFdV06t/xTw0Au10oA9mBPTsxGcrbgUUjKB0y 8rTFXic8y7nvgDatzR8axm4= X-Google-Smtp-Source: APXvYqxRsbnhzjPTVBHYzAGHRJPGuoR5kakVjhHUCKiPBXt2DPWilW2V+8cEN2OZBwmSv56HcHzeyg== X-Received: by 2002:a5d:4446:: with SMTP id x6mr3728372wrr.147.1554379204086; Thu, 04 Apr 2019 05:00:04 -0700 (PDT) Received: from localhost (pD9E51B25.dip0.t-ipconnect.de. [217.229.27.37]) by smtp.gmail.com with ESMTPSA id z17sm20447340wmc.7.2019.04.04.05.00.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 05:00:03 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:35 +0200 Message-Id: <20190404115942.17947-13-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 12/19] ARM: tegra: Unify Tegra186 builds X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Tegra186 build are currently dealt with in very special ways, which is because Tegra186 is fundamentally different in many respects. It is no longer necessary to do many of the low-level programming because early boot firmware will already have taken care of it. Unfortunately, separating Tegra186 builds from the rest in this way makes it difficult to share code with prior generations of Tegra. With all of the low-level programming code behind Kconfig guards, the build for Tegra186 can again be unified. As a side-effect, and partial reason for this change, other Tegra SoC generations can now make use of the code that deals with taking over a boot from earlier bootloaders. This used to be nvtboot, but has been replaced by cboot nowadays. Rename the files and functions related to this to avoid confusion. The implemented protocols are unchanged. Signed-off-by: Thierry Reding --- Changes in v4: - consistently use /chosen/nvidia,ether-mac property Changes in v3: - load cboot DTB address to fdt_addr instead of fdtaddr arch/arm/include/asm/arch-tegra/cboot.h | 39 ++++ arch/arm/mach-tegra/Makefile | 4 +- arch/arm/mach-tegra/board.c | 23 ++ arch/arm/mach-tegra/board186.c | 32 --- arch/arm/mach-tegra/board2.c | 21 ++ .../{tegra186/nvtboot_board.c => cboot.c} | 200 ++++++++++++++++-- .../{tegra186/nvtboot_ll.S => cboot_ll.S} | 12 +- arch/arm/mach-tegra/tegra186/Makefile | 4 - arch/arm/mach-tegra/tegra186/nvtboot_mem.c | 172 --------------- board/nvidia/p2771-0000/p2771-0000.c | 10 +- 10 files changed, 278 insertions(+), 239 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/cboot.h delete mode 100644 arch/arm/mach-tegra/board186.c rename arch/arm/mach-tegra/{tegra186/nvtboot_board.c => cboot.c} (56%) rename arch/arm/mach-tegra/{tegra186/nvtboot_ll.S => cboot_ll.S} (57%) delete mode 100644 arch/arm/mach-tegra/tegra186/nvtboot_mem.c diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h new file mode 100644 index 000000000000..b3441ec178b3 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/cboot.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 NVIDIA Corporation. All rights reserved. + */ + +#ifndef _TEGRA_CBOOT_H_ +#define _TEGRA_CBOOT_H_ + +#ifdef CONFIG_ARM64 +extern unsigned long cboot_boot_x0; + +void cboot_save_boot_params(unsigned long x0, unsigned long x1, + unsigned long x2, unsigned long x3); +int cboot_dram_init(void); +int cboot_dram_init_banksize(void); +ulong cboot_get_usable_ram_top(ulong total_size); +#else +static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1, + unsigned long x2, unsigned long x3) +{ +} + +static inline int cboot_dram_init(void) +{ + return -ENOSYS; +} + +static inline int cboot_dram_init_banksize(void) +{ + return -ENOSYS; +} + +static inline ulong cboot_get_usable_ram_top(ulong total_size) +{ + return 0; +} +#endif + +#endif diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index f8bc65aa8b18..41ba674edff4 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -5,7 +5,6 @@ # (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_TEGRA186 ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-y += cpu.o @@ -20,9 +19,8 @@ obj-$(CONFIG_TEGRA_CLKRST) += clock.o obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o obj-$(CONFIG_TEGRA_PMC) += powergate.o obj-y += xusb-padctl-dummy.o -endif -obj-$(CONFIG_ARM64) += arm64-mmu.o +obj-$(CONFIG_ARM64) += arm64-mmu.o cboot_ll.o cboot.o obj-y += dt-setup.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_GPU) += gpu.o diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 59d2f347485d..c3ba00811e83 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -46,6 +47,21 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, unsigned long r3) { from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; + + /* + * The logic for this is somewhat indirect. The purpose of the marker + * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot + * was loaded from a read-only instance of itself, which is something + * that can happen in secure boot setups. So basically the presence + * of the marker is an indication that U-Boot was loaded by one such + * special variant of U-Boot. Conversely, the absence of the marker + * indicates that this instance of U-Boot was loaded by something + * other than a special U-Boot. This could be SPL, but it could just + * as well be one of any number of other first stage bootloaders. + */ + if (from_spl) + cboot_save_boot_params(r0, r1, r2, r3); + save_boot_params_ret(); } #endif @@ -127,6 +143,13 @@ static phys_size_t query_sdram_size(void) int dram_init(void) { + int err; + + /* try to initialize DRAM from cboot DTB first */ + err = cboot_dram_init(); + if (err == 0) + return 0; + #if IS_ENABLED(CONFIG_TEGRA_MC) /* We do not initialise DRAM here. We just query the size */ gd->ram_size = query_sdram_size(); diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c deleted file mode 100644 index 80b55707e90f..000000000000 --- a/arch/arm/mach-tegra/board186.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. - */ - -#include -#include - -int board_early_init_f(void) -{ - return 0; -} - -__weak int tegra_board_init(void) -{ - return 0; -} - -int board_init(void) -{ - return tegra_board_init(); -} - -__weak int tegra_soc_board_init_late(void) -{ - return 0; -} - -int board_late_init(void) -{ - return tegra_soc_board_init_late(); -} diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index ce1c9346959d..bbc487aa3bf6 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -51,6 +52,7 @@ __weak void pin_mux_mmc(void) {} __weak void gpio_early_init_uart(void) {} __weak void pin_mux_display(void) {} __weak void start_cpu_fan(void) {} +__weak void cboot_late_init(void) {} #if defined(CONFIG_TEGRA_NAND) __weak void pin_mux_nand(void) @@ -243,6 +245,7 @@ int board_late_init(void) } #endif start_cpu_fan(); + cboot_late_init(); return 0; } @@ -337,6 +340,15 @@ static ulong usable_ram_size_below_4g(void) */ int dram_init_banksize(void) { + int err; + + /* try to compute DRAM bank size based on cboot DTB first */ + err = cboot_dram_init_banksize(); + if (err == 0) + return err; + + /* fall back to default DRAM bank size computation */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); @@ -370,5 +382,14 @@ int dram_init_banksize(void) */ ulong board_get_usable_ram_top(ulong total_size) { + ulong ram_top; + + /* try to get top of usable RAM based on cboot DTB first */ + ram_top = cboot_get_usable_ram_top(total_size); + if (ram_top > 0) + return ram_top; + + /* fall back to default usable RAM computation */ + return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_board.c b/arch/arm/mach-tegra/cboot.c similarity index 56% rename from arch/arm/mach-tegra/tegra186/nvtboot_board.c rename to arch/arm/mach-tegra/cboot.c index 83c0e931ea24..3ebf7b055553 100644 --- a/arch/arm/mach-tegra/tegra186/nvtboot_board.c +++ b/arch/arm/mach-tegra/cboot.c @@ -3,14 +3,182 @@ * Copyright (c) 2016-2018, NVIDIA CORPORATION. */ -#include #include #include #include +#include + +#include + #include +#include #include -extern unsigned long nvtboot_boot_x0; +/* + * Size of a region that's large enough to hold the relocated U-Boot and all + * other allocations made around it (stack, heap, page tables, etc.) + * In practice, running "bdinfo" at the shell prompt, the stack reaches about + * 5MB from the address selected for ram_top as of the time of writing, + * so a 16MB region should be plenty. + */ +#define MIN_USABLE_RAM_SIZE SZ_16M +/* + * The amount of space we expect to require for stack usage. Used to validate + * that all reservations fit into the region selected for the relocation target + */ +#define MIN_USABLE_STACK_SIZE SZ_1M + +DECLARE_GLOBAL_DATA_PTR; + +extern struct mm_region tegra_mem_map[]; + +/* + * These variables are written to before relocation, and hence cannot be + * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary. + * The section attribute forces this into .data and avoids this issue. This + * also has the nice side-effect of the content being valid after relocation. + */ + +/* The number of valid entries in ram_banks[] */ +static int ram_bank_count __attribute__((section(".data"))); + +/* + * The usable top-of-RAM for U-Boot. This is both: + * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing. + * b) At the end of a region that has enough space to hold the relocated U-Boot + * and all other allocations made around it (stack, heap, page tables, etc.) + */ +static u64 ram_top __attribute__((section(".data"))); +/* The base address of the region of RAM that ends at ram_top */ +static u64 region_base __attribute__((section(".data"))); + +int cboot_dram_init(void) +{ + unsigned int na, ns; + const void *cboot_blob = (void *)cboot_boot_x0; + int node, len, i; + const u32 *prop; + + if (!cboot_blob) + return -EINVAL; + + na = fdtdec_get_uint(cboot_blob, 0, "#address-cells", 2); + ns = fdtdec_get_uint(cboot_blob, 0, "#size-cells", 2); + + node = fdt_path_offset(cboot_blob, "/memory"); + if (node < 0) { + pr_err("Can't find /memory node in cboot DTB"); + hang(); + } + prop = fdt_getprop(cboot_blob, node, "reg", &len); + if (!prop) { + pr_err("Can't find /memory/reg property in cboot DTB"); + hang(); + } + + /* Calculate the true # of base/size pairs to read */ + len /= 4; /* Convert bytes to number of cells */ + len /= (na + ns); /* Convert cells to number of banks */ + if (len > CONFIG_NR_DRAM_BANKS) + len = CONFIG_NR_DRAM_BANKS; + + /* Parse the /memory node, and save useful entries */ + gd->ram_size = 0; + ram_bank_count = 0; + for (i = 0; i < len; i++) { + u64 bank_start, bank_end, bank_size, usable_bank_size; + + /* Extract raw memory region data from DTB */ + bank_start = fdt_read_number(prop, na); + prop += na; + bank_size = fdt_read_number(prop, ns); + prop += ns; + gd->ram_size += bank_size; + bank_end = bank_start + bank_size; + debug("Bank %d: %llx..%llx (+%llx)\n", i, + bank_start, bank_end, bank_size); + + /* + * Align the bank to MMU section size. This is not strictly + * necessary, since the translation table construction code + * handles page granularity without issue. However, aligning + * the MMU entries reduces the size and number of levels in the + * page table, so is worth it. + */ + bank_start = ROUND(bank_start, SZ_2M); + bank_end = bank_end & ~(SZ_2M - 1); + bank_size = bank_end - bank_start; + debug(" aligned: %llx..%llx (+%llx)\n", + bank_start, bank_end, bank_size); + if (bank_end <= bank_start) + continue; + + /* Record data used to create MMU translation tables */ + ram_bank_count++; + /* Index below is deliberately 1-based to skip MMIO entry */ + tegra_mem_map[ram_bank_count].virt = bank_start; + tegra_mem_map[ram_bank_count].phys = bank_start; + tegra_mem_map[ram_bank_count].size = bank_size; + tegra_mem_map[ram_bank_count].attrs = + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; + + /* Determine best bank to relocate U-Boot into */ + if (bank_end > SZ_4G) + bank_end = SZ_4G; + debug(" end %llx (usable)\n", bank_end); + usable_bank_size = bank_end - bank_start; + debug(" size %llx (usable)\n", usable_bank_size); + if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) && + (bank_end > ram_top)) { + ram_top = bank_end; + region_base = bank_start; + debug("ram top now %llx\n", ram_top); + } + } + + /* Ensure memory map contains the desired sentinel entry */ + tegra_mem_map[ram_bank_count + 1].virt = 0; + tegra_mem_map[ram_bank_count + 1].phys = 0; + tegra_mem_map[ram_bank_count + 1].size = 0; + tegra_mem_map[ram_bank_count + 1].attrs = 0; + + /* Error out if a relocation target couldn't be found */ + if (!ram_top) { + pr_err("Can't find a usable RAM top"); + hang(); + } + + return 0; +} + +int cboot_dram_init_banksize(void) +{ + int i; + + if (ram_bank_count == 0) + return -EINVAL; + + if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) { + pr_err("Reservations exceed chosen region size"); + hang(); + } + + for (i = 0; i < ram_bank_count; i++) { + gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; + gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; + } + +#ifdef CONFIG_PCI + gd->pci_ram_top = ram_top; +#endif + + return 0; +} + +ulong cboot_get_usable_ram_top(ulong total_size) +{ + return ram_top; +} /* * The following few functions run late during the boot process and dynamically @@ -23,8 +191,6 @@ extern unsigned long nvtboot_boot_x0; * list of RAM banks into some private data structure before running. */ -extern struct mm_region tegra_mem_map[]; - static char *gen_varname(const char *var, const char *ext) { size_t len_var = strlen(var); @@ -235,7 +401,7 @@ static void set_calculated_env_vars(void) dump_ram_banks(); #endif - reserve_ram(nvtboot_boot_x0, fdt_totalsize(nvtboot_boot_x0)); + reserve_ram(cboot_boot_x0, fdt_totalsize(cboot_boot_x0)); #ifdef DEBUG printf("RAM after reserving cboot DTB:\n"); @@ -262,7 +428,7 @@ static void set_calculated_env_vars(void) debug("%s: var: %s\n", __func__, var); set_calculated_env_var(var); #ifdef DEBUG - printf("RAM banks affter allocating %s:\n", var); + printf("RAM banks after allocating %s:\n", var); dump_ram_banks(); #endif } @@ -274,7 +440,7 @@ static int set_fdt_addr(void) { int ret; - ret = env_set_hex("fdt_addr", nvtboot_boot_x0); + ret = env_set_hex("fdt_addr", cboot_boot_x0); if (ret) { printf("Failed to set fdt_addr to point at DTB: %d\n", ret); return ret; @@ -284,12 +450,12 @@ static int set_fdt_addr(void) } /* - * Attempt to use /chosen/nvidia,ether-mac in the nvtboot DTB to U-Boot's + * Attempt to use /chosen/nvidia,ether-mac in the cboot DTB to U-Boot's * ethaddr environment variable if possible. */ -static int set_ethaddr_from_nvtboot(void) +static int set_ethaddr_from_cboot(void) { - const void *nvtboot_blob = (void *)nvtboot_boot_x0; + const void *cboot_blob = (void *)cboot_boot_x0; int ret, node, len; const u32 *prop; @@ -297,27 +463,27 @@ static int set_ethaddr_from_nvtboot(void) if (env_get("ethaddr")) return 0; - node = fdt_path_offset(nvtboot_blob, "/chosen"); + node = fdt_path_offset(cboot_blob, "/chosen"); if (node < 0) { - printf("Can't find /chosen node in nvtboot DTB\n"); + printf("Can't find /chosen node in cboot DTB\n"); return node; } - prop = fdt_getprop(nvtboot_blob, node, "nvidia,ether-mac", &len); + prop = fdt_getprop(cboot_blob, node, "nvidia,ether-mac", &len); if (!prop) { - printf("Can't find nvidia,ether-mac property in nvtboot DTB\n"); + printf("Can't find nvidia,ether-mac property in cboot DTB\n"); return -ENOENT; } ret = env_set("ethaddr", (void *)prop); if (ret) { - printf("Failed to set ethaddr from nvtboot DTB: %d\n", ret); + printf("Failed to set ethaddr from cboot DTB: %d\n", ret); return ret; } return 0; } -int tegra_soc_board_init_late(void) +int cboot_late_init(void) { set_calculated_env_vars(); /* @@ -326,7 +492,7 @@ int tegra_soc_board_init_late(void) */ set_fdt_addr(); /* Ignore errors here; not all cases care about Ethernet addresses */ - set_ethaddr_from_nvtboot(); + set_ethaddr_from_cboot(); return 0; } diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S b/arch/arm/mach-tegra/cboot_ll.S similarity index 57% rename from arch/arm/mach-tegra/tegra186/nvtboot_ll.S rename to arch/arm/mach-tegra/cboot_ll.S index aa7a863d9702..4c9ddacc2b39 100644 --- a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S +++ b/arch/arm/mach-tegra/cboot_ll.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Save nvtboot-related boot-time CPU state + * Save cboot-related boot-time CPU state * * (C) Copyright 2015-2016 NVIDIA Corporation */ @@ -9,12 +9,12 @@ #include .align 8 -.globl nvtboot_boot_x0 -nvtboot_boot_x0: +.globl cboot_boot_x0 +cboot_boot_x0: .dword 0 -ENTRY(save_boot_params) - adr x8, nvtboot_boot_x0 +ENTRY(cboot_save_boot_params) + adr x8, cboot_boot_x0 str x0, [x8] b save_boot_params_ret -ENDPROC(save_boot_params) +ENDPROC(cboot_save_boot_params) diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile index 56f3378ecea3..3a2405027704 100644 --- a/arch/arm/mach-tegra/tegra186/Makefile +++ b/arch/arm/mach-tegra/tegra186/Makefile @@ -2,8 +2,4 @@ # # SPDX-License-Identifier: GPL-2.0 -obj-y += ../board186.o obj-y += cache.o -obj-y += nvtboot_board.o -obj-y += nvtboot_ll.o -obj-y += nvtboot_mem.o diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c deleted file mode 100644 index 62142821a595..000000000000 --- a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. - */ - -#include -#include -#include -#include -#include -#include - -/* - * Size of a region that's large enough to hold the relocated U-Boot and all - * other allocations made around it (stack, heap, page tables, etc.) - * In practice, running "bdinfo" at the shell prompt, the stack reaches about - * 5MB from the address selected for ram_top as of the time of writing, - * so a 16MB region should be plenty. - */ -#define MIN_USABLE_RAM_SIZE SZ_16M -/* - * The amount of space we expect to require for stack usage. Used to validate - * that all reservations fit into the region selected for the relocation target - */ -#define MIN_USABLE_STACK_SIZE SZ_1M - -DECLARE_GLOBAL_DATA_PTR; - -extern unsigned long nvtboot_boot_x0; -extern struct mm_region tegra_mem_map[]; - -/* - * These variables are written to before relocation, and hence cannot be - * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary. - * The section attribute forces this into .data and avoids this issue. This - * also has the nice side-effect of the content being valid after relocation. - */ - -/* The number of valid entries in ram_banks[] */ -static int ram_bank_count __attribute__((section(".data"))); - -/* - * The usable top-of-RAM for U-Boot. This is both: - * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing. - * b) At the end of a region that has enough space to hold the relocated U-Boot - * and all other allocations made around it (stack, heap, page tables, etc.) - */ -static u64 ram_top __attribute__((section(".data"))); -/* The base address of the region of RAM that ends at ram_top */ -static u64 region_base __attribute__((section(".data"))); - -int dram_init(void) -{ - unsigned int na, ns; - const void *nvtboot_blob = (void *)nvtboot_boot_x0; - int node, len, i; - const u32 *prop; - - na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2); - ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2); - - node = fdt_path_offset(nvtboot_blob, "/memory"); - if (node < 0) { - pr_err("Can't find /memory node in nvtboot DTB"); - hang(); - } - prop = fdt_getprop(nvtboot_blob, node, "reg", &len); - if (!prop) { - pr_err("Can't find /memory/reg property in nvtboot DTB"); - hang(); - } - - /* Calculate the true # of base/size pairs to read */ - len /= 4; /* Convert bytes to number of cells */ - len /= (na + ns); /* Convert cells to number of banks */ - if (len > CONFIG_NR_DRAM_BANKS) - len = CONFIG_NR_DRAM_BANKS; - - /* Parse the /memory node, and save useful entries */ - gd->ram_size = 0; - ram_bank_count = 0; - for (i = 0; i < len; i++) { - u64 bank_start, bank_end, bank_size, usable_bank_size; - - /* Extract raw memory region data from DTB */ - bank_start = fdt_read_number(prop, na); - prop += na; - bank_size = fdt_read_number(prop, ns); - prop += ns; - gd->ram_size += bank_size; - bank_end = bank_start + bank_size; - debug("Bank %d: %llx..%llx (+%llx)\n", i, - bank_start, bank_end, bank_size); - - /* - * Align the bank to MMU section size. This is not strictly - * necessary, since the translation table construction code - * handles page granularity without issue. However, aligning - * the MMU entries reduces the size and number of levels in the - * page table, so is worth it. - */ - bank_start = ROUND(bank_start, SZ_2M); - bank_end = bank_end & ~(SZ_2M - 1); - bank_size = bank_end - bank_start; - debug(" aligned: %llx..%llx (+%llx)\n", - bank_start, bank_end, bank_size); - if (bank_end <= bank_start) - continue; - - /* Record data used to create MMU translation tables */ - ram_bank_count++; - /* Index below is deliberately 1-based to skip MMIO entry */ - tegra_mem_map[ram_bank_count].virt = bank_start; - tegra_mem_map[ram_bank_count].phys = bank_start; - tegra_mem_map[ram_bank_count].size = bank_size; - tegra_mem_map[ram_bank_count].attrs = - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; - - /* Determine best bank to relocate U-Boot into */ - if (bank_end > SZ_4G) - bank_end = SZ_4G; - debug(" end %llx (usable)\n", bank_end); - usable_bank_size = bank_end - bank_start; - debug(" size %llx (usable)\n", usable_bank_size); - if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) && - (bank_end > ram_top)) { - ram_top = bank_end; - region_base = bank_start; - debug("ram top now %llx\n", ram_top); - } - } - - /* Ensure memory map contains the desired sentinel entry */ - tegra_mem_map[ram_bank_count + 1].virt = 0; - tegra_mem_map[ram_bank_count + 1].phys = 0; - tegra_mem_map[ram_bank_count + 1].size = 0; - tegra_mem_map[ram_bank_count + 1].attrs = 0; - - /* Error out if a relocation target couldn't be found */ - if (!ram_top) { - pr_err("Can't find a usable RAM top"); - hang(); - } - - return 0; -} - -int dram_init_banksize(void) -{ - int i; - - if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) { - pr_err("Reservations exceed chosen region size"); - hang(); - } - - for (i = 0; i < ram_bank_count; i++) { - gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; - gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; - } - -#ifdef CONFIG_PCI - gd->pci_ram_top = ram_top; -#endif - - return 0; -} - -ulong board_get_usable_ram_top(ulong total_size) -{ - return ram_top; -} diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index 496e8a02111e..6f88010c18c3 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -7,7 +7,7 @@ #include #include "../p2571/max77620_init.h" -int tegra_board_init(void) +void pin_mux_mmc(void) { struct udevice *dev; uchar val; @@ -18,19 +18,18 @@ int tegra_board_init(void) ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); if (ret) { printf("%s: Cannot find MAX77620 I2C chip\n", __func__); - return ret; + return; } /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ val = 0xF2; ret = dm_i2c_write(dev, MAX77620_CNFG1_L3_REG, &val, 1); if (ret) { printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); - return ret; + return; } - - return 0; } +#ifdef CONFIG_PCI_TEGRA int tegra_pcie_board_init(void) { struct udevice *dev; @@ -52,3 +51,4 @@ int tegra_pcie_board_init(void) return 0; } +#endif From patchwork Thu Apr 4 11:59:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077211 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; 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[217.229.27.37]) by smtp.gmail.com with ESMTPSA id a9sm14672598wrt.29.2019.04.04.05.00.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 05:00:04 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:36 +0200 Message-Id: <20190404115942.17947-14-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 13/19] ARM: tegra: Implement cboot_save_boot_params() in C X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding This is easier to deal with and works just as well for this simple function. Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/cboot.c | 12 ++++++++++++ arch/arm/mach-tegra/cboot_ll.S | 20 -------------------- 3 files changed, 13 insertions(+), 21 deletions(-) delete mode 100644 arch/arm/mach-tegra/cboot_ll.S diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 41ba674edff4..7165d70a60da 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o obj-$(CONFIG_TEGRA_PMC) += powergate.o obj-y += xusb-padctl-dummy.o -obj-$(CONFIG_ARM64) += arm64-mmu.o cboot_ll.o cboot.o +obj-$(CONFIG_ARM64) += arm64-mmu.o cboot.o obj-y += dt-setup.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_GPU) += gpu.o diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index 3ebf7b055553..a302ca45f39b 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -52,6 +52,18 @@ static u64 ram_top __attribute__((section(".data"))); /* The base address of the region of RAM that ends at ram_top */ static u64 region_base __attribute__((section(".data"))); +/* + * Explicitly put this in the .data section because it is written before the + * .bss section is zeroed out but it needs to persist. + */ +unsigned long cboot_boot_x0 __attribute__((section(".data"))); + +void cboot_save_boot_params(unsigned long x0, unsigned long x1, + unsigned long x2, unsigned long x3) +{ + cboot_boot_x0 = x0; +} + int cboot_dram_init(void) { unsigned int na, ns; diff --git a/arch/arm/mach-tegra/cboot_ll.S b/arch/arm/mach-tegra/cboot_ll.S deleted file mode 100644 index 4c9ddacc2b39..000000000000 --- a/arch/arm/mach-tegra/cboot_ll.S +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Save cboot-related boot-time CPU state - * - * (C) Copyright 2015-2016 NVIDIA Corporation - */ - -#include -#include - -.align 8 -.globl cboot_boot_x0 -cboot_boot_x0: - .dword 0 - -ENTRY(cboot_save_boot_params) - adr x8, cboot_boot_x0 - str x0, [x8] - b save_boot_params_ret -ENDPROC(cboot_save_boot_params) From patchwork Thu Apr 4 11:59:37 2019 Content-Type: text/plain; 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[217.229.27.37]) by smtp.gmail.com with ESMTPSA id y125sm33640519wmc.39.2019.04.04.05.00.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 05:00:06 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:37 +0200 Message-Id: <20190404115942.17947-15-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 14/19] ARM: tegra: Implement cboot_get_ethaddr() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding This function will attempt to look up an ethernet address in the DTB that was passed in from cboot. It does so by first trying to locate the primary ethernet device for the board (identified by the "ethernet" alias) and if found, reads the "local-mac-address" property. If the "ethernet" alias does not exist, or if it points to a device tree node that doesn't exist, or if the device tree node that it points to does not have a "local-mac-address" property or if the value is invalid, it will fall back to the legacy mechanism of looking for the MAC address stored in the "nvidia,ethernet-mac" or "nvidia,ether-mac" properties of the "/chosen" node. Signed-off-by: Thierry Reding --- Changes in v4: - also check the /chosen/nvidia,ethernet-mac property for compatibility with Tegra210 Changes in v2: - make dummy static inline to avoid duplicate definitions arch/arm/include/asm/arch-tegra/cboot.h | 6 ++ arch/arm/mach-tegra/cboot.c | 92 ++++++++++++++++++++----- 2 files changed, 81 insertions(+), 17 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h index b3441ec178b3..021c24617575 100644 --- a/arch/arm/include/asm/arch-tegra/cboot.h +++ b/arch/arm/include/asm/arch-tegra/cboot.h @@ -14,6 +14,7 @@ void cboot_save_boot_params(unsigned long x0, unsigned long x1, int cboot_dram_init(void); int cboot_dram_init_banksize(void); ulong cboot_get_usable_ram_top(ulong total_size); +int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]); #else static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1, unsigned long x2, unsigned long x3) @@ -34,6 +35,11 @@ static inline ulong cboot_get_usable_ram_top(ulong total_size) { return 0; } + +static inline int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]) +{ + return -ENOSYS; +} #endif #endif diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index a302ca45f39b..6c6d06d89a5d 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -465,46 +466,103 @@ static int set_fdt_addr(void) * Attempt to use /chosen/nvidia,ether-mac in the cboot DTB to U-Boot's * ethaddr environment variable if possible. */ -static int set_ethaddr_from_cboot(void) +static int cboot_get_ethaddr_legacy(const void *fdt, uint8_t mac[ETH_ALEN]) { - const void *cboot_blob = (void *)cboot_boot_x0; - int ret, node, len; - const u32 *prop; - - /* Already a valid address in the environment? If so, keep it */ - if (env_get("ethaddr")) - return 0; - - node = fdt_path_offset(cboot_blob, "/chosen"); + const char *const properties[] = { + "nvidia,ethernet-mac", + "nvidia,ether-mac", + }; + const char *prop; + unsigned int i; + int node, len; + + node = fdt_path_offset(fdt, "/chosen"); if (node < 0) { printf("Can't find /chosen node in cboot DTB\n"); return node; } - prop = fdt_getprop(cboot_blob, node, "nvidia,ether-mac", &len); + + for (i = 0; i < ARRAY_SIZE(properties); i++) { + prop = fdt_getprop(fdt, node, properties[i], &len); + if (prop) + break; + } + if (!prop) { - printf("Can't find nvidia,ether-mac property in cboot DTB\n"); + printf("Can't find Ethernet MAC address in cboot DTB\n"); return -ENOENT; } - ret = env_set("ethaddr", (void *)prop); - if (ret) { - printf("Failed to set ethaddr from cboot DTB: %d\n", ret); - return ret; + eth_parse_enetaddr(prop, mac); + + if (!is_valid_ethaddr(mac)) { + printf("Invalid MAC address: %s\n", prop); + return -EINVAL; } + debug("Legacy MAC address: %pM\n", mac); + return 0; } +int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]) +{ + int node, len, err = 0; + const uchar *prop; + const char *path; + + path = fdt_get_alias(fdt, "ethernet"); + if (!path) { + err = -ENOENT; + goto out; + } + + debug("ethernet alias found: %s\n", path); + + node = fdt_path_offset(fdt, path); + if (node < 0) { + err = -ENOENT; + goto out; + } + + prop = fdt_getprop(fdt, node, "local-mac-address", &len); + if (!prop) { + err = -ENOENT; + goto out; + } + + if (len != ETH_ALEN) { + err = -EINVAL; + goto out; + } + + debug("MAC address: %pM\n", prop); + memcpy(mac, prop, ETH_ALEN); + +out: + if (err < 0) + err = cboot_get_ethaddr_legacy(fdt, mac); + + return err; +} + int cboot_late_init(void) { + const void *fdt = (const void *)cboot_boot_x0; + uint8_t mac[ETH_ALEN]; + int err; + set_calculated_env_vars(); /* * Ignore errors here; the value may not be used depending on * extlinux.conf or boot script content. */ set_fdt_addr(); + /* Ignore errors here; not all cases care about Ethernet addresses */ - set_ethaddr_from_cboot(); + err = cboot_get_ethaddr(fdt, mac); + if (!err) + eth_env_set_enetaddr("ethaddr", mac); return 0; } From patchwork Thu Apr 4 11:59:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077212 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ekfjenVK"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44Zhcq2jTGz9sPd for ; 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[217.229.27.37]) by smtp.gmail.com with ESMTPSA id q3sm27367268wrr.75.2019.04.04.05.00.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 05:00:07 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:38 +0200 Message-Id: <20190404115942.17947-16-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 15/19] ARM: tegra: Enable position independent build for 64-bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Note that U-Boot is always chainloaded from cboot starting with L4T release 28. cboot always loads U-Boot to a fixed address, so making the builds position independent isn't strictly necessary. However, position independent builds can be convenient because if U-Boot is ever loaded to an address different from its link address, it will still be able to boot. Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/Kconfig | 1 + configs/e2220-1170_defconfig | 2 +- configs/p2371-0000_defconfig | 2 +- configs/p2371-2180_defconfig | 2 +- configs/p2571_defconfig | 2 +- 5 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index faa73559fd42..97e22ead5985 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -87,6 +87,7 @@ config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" select ARM64 select LINUX_KERNEL_IMAGE_HEADER + select POSITION_INDEPENDENT select TEGRA_COMMON if TEGRA_ARMV8_COMMON diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig index af3f80edb117..baabb0ccf8cc 100644 --- a/configs/e2220-1170_defconfig +++ b/configs/e2220-1170_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TEGRA=y -CONFIG_SYS_TEXT_BASE=0x80110000 +CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_TEGRA210=y CONFIG_NR_DRAM_BANKS=2 CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index 6b564366a825..aa8b73a2ba08 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TEGRA=y -CONFIG_SYS_TEXT_BASE=0x80110000 +CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_TEGRA210=y CONFIG_TARGET_P2371_0000=y CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index a790cd83b82d..4923d330de6c 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TEGRA=y -CONFIG_SYS_TEXT_BASE=0x80110000 +CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_TEGRA210=y CONFIG_TARGET_P2371_2180=y CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index e48e0a1a14ec..8e9c45690dce 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TEGRA=y -CONFIG_SYS_TEXT_BASE=0x80110000 +CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_TEGRA210=y CONFIG_TARGET_P2571=y CONFIG_NR_DRAM_BANKS=2 From patchwork Thu Apr 4 11:59:39 2019 Content-Type: text/plain; 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[217.229.27.37]) by smtp.gmail.com with ESMTPSA id 11sm9073904wmk.17.2019.04.04.05.00.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 05:00:09 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:39 +0200 Message-Id: <20190404115942.17947-17-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 16/19] p2371-2180: Pass Ethernet MAC to the kernel X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Pass the ethernet MAC address to the kernel upon boot. This passes both the local-mac-address property (as passed to U-Boot from cboot) and the currently set MAC address via the mac-address property. The latter will only be set if it is different from the address that was already passed via the local-mac-address property. Signed-off-by: Thierry Reding --- board/nvidia/p2371-2180/p2371-2180.c | 50 ++++++++++++++++++++++++++++ configs/p2371-2180_defconfig | 1 + 2 files changed, 51 insertions(+) diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 212037da5ac0..a444d692d7ea 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -5,9 +5,12 @@ */ #include +#include #include +#include #include #include +#include #include "../p2571/max77620_init.h" #include "pinmux-config-p2371-2180.h" @@ -94,3 +97,50 @@ int tegra_pcie_board_init(void) return 0; } #endif /* PCI */ + +static void ft_mac_address_setup(void *fdt) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; + const char *path; + int offset, err; + + err = cboot_get_ethaddr(cboot_fdt, local_mac); + if (err < 0) + memset(local_mac, 0, ETH_ALEN); + + path = fdt_get_alias(fdt, "ethernet"); + if (!path) + return; + + debug("ethernet alias found: %s\n", path); + + offset = fdt_path_offset(fdt, path); + if (offset < 0) { + printf("ethernet alias points to absent node %s\n", path); + return; + } + + if (is_valid_ethaddr(local_mac)) { + err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, + ETH_ALEN); + if (!err) + debug("Local MAC address set: %pM\n", local_mac); + } + + if (eth_env_get_enetaddr("ethaddr", mac)) { + if (memcmp(local_mac, mac, ETH_ALEN) != 0) { + err = fdt_setprop(fdt, offset, "mac-address", mac, + ETH_ALEN); + if (!err) + debug("MAC address set: %pM\n", mac); + } + } +} + +int ft_board_setup(void *fdt, bd_t *bd) +{ + ft_mac_address_setup(fdt); + + return 0; +} diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 4923d330de6c..0ee4913a0469 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -5,6 +5,7 @@ CONFIG_TEGRA210=y CONFIG_TARGET_P2371_2180=y CONFIG_NR_DRAM_BANKS=2 CONFIG_OF_SYSTEM_SETUP=y +CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # " From patchwork Thu Apr 4 11:59:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077208 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OnHTDcco"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44Zhbs1c9fz9sPd for ; Thu, 4 Apr 2019 23:10:33 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DB26AC21E35; Thu, 4 Apr 2019 12:06:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1BC41C21EBF; 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[217.229.27.37]) by smtp.gmail.com with ESMTPSA id 7sm67028687wrc.81.2019.04.04.05.00.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 05:00:10 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:40 +0200 Message-Id: <20190404115942.17947-18-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 17/19] p2771-0000: Pass Ethernet MAC to the kernel X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Pass the ethernet MAC address to the kernel upon boot. This passes both the local-mac-address property (as passed to U-Boot from cboot) and the currently set MAC address via the mac-address property. The latter will only be set if it is different from the address that was already passed via the local-mac-address property. Signed-off-by: Thierry Reding --- board/nvidia/p2771-0000/p2771-0000.c | 43 ++++++++++++++++++++++++++++ configs/p2771-0000-000_defconfig | 1 + configs/p2771-0000-500_defconfig | 1 + 3 files changed, 45 insertions(+) diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index 6f88010c18c3..fe22067f6571 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -4,7 +4,10 @@ */ #include +#include #include +#include +#include #include "../p2571/max77620_init.h" void pin_mux_mmc(void) @@ -52,3 +55,43 @@ int tegra_pcie_board_init(void) return 0; } #endif + +int ft_board_setup(void *fdt, bd_t *bd) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; + const char *path; + int offset, err; + + err = cboot_get_ethaddr(cboot_fdt, local_mac); + if (err < 0) + memset(local_mac, 0, ETH_ALEN); + + path = fdt_get_alias(fdt, "ethernet"); + if (!path) + return 0; + + debug("ethernet alias found: %s\n", path); + + offset = fdt_path_offset(fdt, path); + if (offset < 0) + return 0; + + if (is_valid_ethaddr(local_mac)) { + err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, + ETH_ALEN); + if (!err) + debug("Local MAC address set: %pM\n", local_mac); + } + + if (eth_env_get_enetaddr("ethaddr", mac)) { + if (memcmp(local_mac, mac, ETH_ALEN) != 0) { + err = fdt_setprop(fdt, offset, "mac-address", mac, + ETH_ALEN); + if (!err) + debug("MAC address set: %pM\n", mac); + } + } + + return 0; +} diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index ad0802067e73..91896e39a10f 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_TEGRA186=y CONFIG_NR_DRAM_BANKS=1026 CONFIG_OF_SYSTEM_SETUP=y +CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # " diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index 459b67fd195f..20d4393838d6 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_TEGRA186=y CONFIG_NR_DRAM_BANKS=1026 CONFIG_OF_SYSTEM_SETUP=y +CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # " From patchwork Thu Apr 4 11:59:41 2019 Content-Type: text/plain; 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[217.229.27.37]) by smtp.gmail.com with ESMTPSA id a23sm16178958wmm.46.2019.04.04.05.00.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 05:00:12 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:41 +0200 Message-Id: <20190404115942.17947-19-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 18/19] lib: Implement strndup() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Signed-off-by: Thierry Reding --- include/linux/string.h | 1 + lib/string.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/linux/string.h b/include/linux/string.h index 36066207392e..5d63be4ce5b0 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -94,6 +94,7 @@ size_t strcspn(const char *s, const char *reject); #ifndef __HAVE_ARCH_STRDUP extern char * strdup(const char *); #endif +extern char * strndup(const char *, size_t); #ifndef __HAVE_ARCH_STRSWAB extern char * strswab(const char *); #endif diff --git a/lib/string.c b/lib/string.c index af17c16f616d..9b779ddc3bbe 100644 --- a/lib/string.c +++ b/lib/string.c @@ -326,6 +326,29 @@ char * strdup(const char *s) } #endif +char * strndup(const char *s, size_t n) +{ + size_t len; + char *new; + + if (s == NULL) + return NULL; + + len = strlen(s); + + if (n < len) + len = n; + + new = malloc(len + 1); + if (new == NULL) + return NULL; + + strncpy(new, s, len); + new[len] = '\0'; + + return new; +} + #ifndef __HAVE_ARCH_STRSPN /** * strspn - Calculate the length of the initial substring of @s which only From patchwork Thu Apr 4 11:59:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1077205 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[217.229.27.37]) by smtp.gmail.com with ESMTPSA id o20sm19297048wmh.21.2019.04.04.05.00.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Apr 2019 05:00:13 -0700 (PDT) From: Thierry Reding To: Tom Warren Date: Thu, 4 Apr 2019 13:59:42 +0200 Message-Id: <20190404115942.17947-20-thierry.reding@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190404115942.17947-1-thierry.reding@gmail.com> References: <20190404115942.17947-1-thierry.reding@gmail.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Stephen Warren , Jonathan Hunter Subject: [U-Boot] [PATCH v4 19/19] ARM: tegra: Import cbootargs value from cboot DTB X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Read the boot arguments passed by cboot via the /chosen/bootargs property and store it in the cbootargs environment variable. Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/cboot.c | 47 +++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index 6c6d06d89a5d..3f42ffeb73c0 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -8,7 +8,9 @@ #include #include #include +#include +#include #include #include @@ -546,10 +548,49 @@ out: return err; } +static char *strip(const char *ptr) +{ + const char *end; + + while (*ptr && isblank(*ptr)) + ptr++; + + /* empty string */ + if (*ptr == '\0') + return strdup(ptr); + + end = ptr; + + while (end[1]) + end++; + + while (isblank(*end)) + end--; + + return strndup(ptr, end - ptr + 1); +} + +static char *cboot_get_bootargs(const void *fdt) +{ + const char *args; + int offset, len; + + offset = fdt_path_offset(fdt, "/chosen"); + if (offset < 0) + return NULL; + + args = fdt_getprop(fdt, offset, "bootargs", &len); + if (!args) + return NULL; + + return strip(args); +} + int cboot_late_init(void) { const void *fdt = (const void *)cboot_boot_x0; uint8_t mac[ETH_ALEN]; + char *bootargs; int err; set_calculated_env_vars(); @@ -564,5 +605,11 @@ int cboot_late_init(void) if (!err) eth_env_set_enetaddr("ethaddr", mac); + bootargs = cboot_get_bootargs(fdt); + if (bootargs) { + env_set("cbootargs", bootargs); + free(bootargs); + } + return 0; }