diff mbox

ARC: Support syscall ABI v4

Message ID 1471385067-1671-1-git-send-email-vgupta@synopsys.com
State New
Headers show

Commit Message

Vineet Gupta Aug. 16, 2016, 10:04 p.m. UTC
The syscall ABI includes the gcc functional calling ABI since a syscall
implies userland caller and kernel callee.

The current gcc ABI (v3) for ARCv2 ISA required 64-bit data be passed in
even-odd register pairs, (potentially punching reg holes when passing such
values as args). This was partly driven by the fact that the double-word
LDD/STD instructions in ARCv2 expect the register alignment and thus gcc
forcing this avoids extra MOV at the cost of a few unused register (which we
have plenty anyways).

This however was rejected as part of upstreaming gcc port to HS. So the new
ABI v4 doesn't enforce the even-odd reg restriction.

Do note that for ARCompact ISA builds v3 and v4 are practically the same in
terms of gcc code generation.

This change is dormant for now (gcc 4.8.x based tools) and will only kick
in with switch to gcc 6.x based tools.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
---
 libc/sysdeps/linux/arc/bits/uClibc_arch_features.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Comments

Waldemar Brodkorb Aug. 18, 2016, 4:22 a.m. UTC | #1
Hi Vineet,
Vineet Gupta wrote,

> The syscall ABI includes the gcc functional calling ABI since a syscall
> implies userland caller and kernel callee.
> 
> The current gcc ABI (v3) for ARCv2 ISA required 64-bit data be passed in
> even-odd register pairs, (potentially punching reg holes when passing such
> values as args). This was partly driven by the fact that the double-word
> LDD/STD instructions in ARCv2 expect the register alignment and thus gcc
> forcing this avoids extra MOV at the cost of a few unused register (which we
> have plenty anyways).
> 
> This however was rejected as part of upstreaming gcc port to HS. So the new
> ABI v4 doesn't enforce the even-odd reg restriction.
> 
> Do note that for ARCompact ISA builds v3 and v4 are practically the same in
> terms of gcc code generation.
> 
> This change is dormant for now (gcc 4.8.x based tools) and will only kick
> in with switch to gcc 6.x based tools.
> 
> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

Thanks, applied and pushed,
 Waldemar
diff mbox

Patch

diff --git a/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h b/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h
index 51607240cd82..94e089d5dfa8 100755
--- a/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h
+++ b/libc/sysdeps/linux/arc/bits/uClibc_arch_features.h
@@ -41,8 +41,14 @@ 
 /* The default ';' is a comment on ARC. */
 #define __UCLIBC_ASM_LINE_SEP__ `
 
-/* does your target align 64bit values in register pairs ? (32bit arches only) */
-#if defined(__A7__)
+/* does your target align 64bit values in register pairs ? (32bit arches only)
+ *  - ARC700 never had any constraint on reg pairs (even if ABI v3)
+ *  - Inital HS ABI (v3: non upstream gcc) had 64-bit data aligned in even-odd
+ *     reg pairs (thus allowed reg holes when passing such args to calls)
+ *  - Upstream gcc (6.x) HS ABI doesn't have that restriction
+ */
+
+#if defined(__A7__) || (__GNUC__ > 4)
 #undef __UCLIBC_SYSCALL_ALIGN_64BIT__
 #else
 #define __UCLIBC_SYSCALL_ALIGN_64BIT__