From patchwork Wed Feb 18 12:11:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 440963 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from fraxinus.osuosl.org (fraxinus.osuosl.org [140.211.166.137]) by ozlabs.org (Postfix) with ESMTP id CE11D140079 for ; Wed, 18 Feb 2015 23:12:00 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id DF01DA31AE; Wed, 18 Feb 2015 12:11:59 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id f8hELLlvj0GA; Wed, 18 Feb 2015 12:11:57 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by fraxinus.osuosl.org (Postfix) with ESMTP id BA8AEA31E9; Wed, 18 Feb 2015 12:11:57 +0000 (UTC) X-Original-To: uclibc@lists.busybox.net Delivered-To: uclibc@osuosl.org Received: from silver.osuosl.org (silver.osuosl.org [140.211.166.136]) by ash.osuosl.org (Postfix) with ESMTP id 0BB9D1C0F70 for ; Wed, 18 Feb 2015 12:11:56 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by silver.osuosl.org (Postfix) with ESMTP id EF35B3370A for ; Wed, 18 Feb 2015 12:11:55 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from silver.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EnlbpWNlu89m for ; Wed, 18 Feb 2015 12:11:55 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from smtprelay.synopsys.com (us01smtprelay-2.synopsys.com [198.182.60.111]) by silver.osuosl.org (Postfix) with ESMTPS id 3189B336F1 for ; Wed, 18 Feb 2015 12:11:55 +0000 (UTC) Received: from us02secmta1.synopsys.com (us02secmta1.synopsys.com [10.12.235.96]) by smtprelay.synopsys.com (Postfix) with ESMTP id B097310C0DFA for ; Wed, 18 Feb 2015 04:11:54 -0800 (PST) Received: from us02secmta1.internal.synopsys.com (us02secmta1.internal.synopsys.com [127.0.0.1]) by us02secmta1.internal.synopsys.com (Service) with ESMTP id A45034E213 for ; Wed, 18 Feb 2015 04:11:54 -0800 (PST) Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by us02secmta1.internal.synopsys.com (Service) with ESMTP id 6C9A64E202 for ; Wed, 18 Feb 2015 04:11:54 -0800 (PST) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 61706343 for ; Wed, 18 Feb 2015 04:11:54 -0800 (PST) Received: from US01WEHTC2.internal.synopsys.com (us01wehtc2-vip.internal.synopsys.com [10.12.239.238]) by mailhost.synopsys.com (Postfix) with ESMTP id 59F72342 for ; Wed, 18 Feb 2015 04:11:54 -0800 (PST) Received: from US02VWCASHYB1.internal.synopsys.com (10.12.237.254) by US01WEHTC2.internal.synopsys.com (10.12.239.237) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 18 Feb 2015 04:11:54 -0800 Received: from IN01WEHTCA.internal.synopsys.com (10.144.199.104) by US02VWCASHYB1.internal.synopsys.com (10.12.237.251) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 18 Feb 2015 04:11:53 -0800 Received: from IN01WEHTCB.internal.synopsys.com (10.144.199.105) by IN01WEHTCA.internal.synopsys.com (10.144.199.103) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 18 Feb 2015 17:41:51 +0530 Received: from vineetg-E7440.internal.synopsys.com (10.12.196.223) by IN01WEHTCB.internal.synopsys.com (10.144.199.243) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 18 Feb 2015 17:41:50 +0530 From: Vineet Gupta To: Subject: [PATCH 3/4] posix_fadvise: handle 2 variants for SYSCALL_ALIGN_64BIT Date: Wed, 18 Feb 2015 17:41:06 +0530 Message-ID: <1424261467-7934-4-git-send-email-vgupta@synopsys.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1424261467-7934-1-git-send-email-vgupta@synopsys.com> References: <1424261467-7934-1-git-send-email-vgupta@synopsys.com> MIME-Version: 1.0 X-Originating-IP: [10.12.196.223] Cc: Vineet Gupta X-BeenThere: uclibc@uclibc.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "Discussion and development of uClibc \(the embedded C library\)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: uclibc-bounces@uclibc.org Sender: "uClibc" arm/powerpc/xtensa pass @advice as 2nd arg to syscall (vs. canonical 4th) Current code however does this for UCLIBC_SYSCALL_ALIGN_64BIT (which powerpc/xtensa) happen to define. This is not true for ARCv2 ISA and possibly other arch of future which uses the standard syscall handler in kernel despite 64-bit even register requirement. Signed-off-by: Vineet Gupta --- libc/sysdeps/linux/common/posix_fadvise.c | 6 +++++- libc/sysdeps/linux/common/posix_fadvise64.c | 11 ++++++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/libc/sysdeps/linux/common/posix_fadvise.c b/libc/sysdeps/linux/common/posix_fadvise.c index 14bbeeea13bc..a5810787efe4 100644 --- a/libc/sysdeps/linux/common/posix_fadvise.c +++ b/libc/sysdeps/linux/common/posix_fadvise.c @@ -41,9 +41,13 @@ int posix_fadvise(int fd, off_t offset, off_t len, int advice) # if __WORDSIZE == 64 ret = INTERNAL_SYSCALL(fadvise64_64, err, 4, fd, offset, len, advice); # else -# if defined(__UCLIBC_SYSCALL_ALIGN_64BIT__) || defined(__arm__) +# if defined (__arm__) || \ + (defined(__UCLIBC_SYSCALL_ALIGN_64BIT__) && (defined(__powerpc__) || defined(__xtensa__))) ret = INTERNAL_SYSCALL(fadvise64_64, err, 6, fd, advice, OFF_HI_LO (offset), OFF_HI_LO (len)); +# elif defined(__UCLIBC_SYSCALL_ALIGN_64BIT__) + ret = INTERNAL_SYSCALL(fadvise64_64, err, 7, fd, 0, + OFF_HI_LO (offset), OFF_HI_LO (len), advice); # else ret = INTERNAL_SYSCALL(fadvise64_64, err, 6, fd, OFF_HI_LO (offset), OFF_HI_LO (len), advice); diff --git a/libc/sysdeps/linux/common/posix_fadvise64.c b/libc/sysdeps/linux/common/posix_fadvise64.c index 5d8989121871..8a1b9ebb16d2 100644 --- a/libc/sysdeps/linux/common/posix_fadvise64.c +++ b/libc/sysdeps/linux/common/posix_fadvise64.c @@ -24,9 +24,18 @@ int posix_fadvise64(int fd, off64_t offset, off64_t len, int advice) { INTERNAL_SYSCALL_DECL (err); /* ARM has always been funky. */ -# if defined(__UCLIBC_SYSCALL_ALIGN_64BIT__) || defined(__arm__) +#if defined (__arm__) || \ + (defined(__UCLIBC_SYSCALL_ALIGN_64BIT__) && (defined(__powerpc__) || defined(__xtensa__))) + /* arch with 64-bit data in even reg alignment #1: [powerpc/xtensa] + * custom syscall handler (rearranges @advice to avoid register hole punch) */ int ret = INTERNAL_SYSCALL (fadvise64_64, err, 6, fd, advice, OFF64_HI_LO (offset), OFF64_HI_LO (len)); +#elif defined(__UCLIBC_SYSCALL_ALIGN_64BIT__) + /* arch with 64-bit data in even reg alignment #2: [arc(HS)/others-in-future] + * stock syscall handler in kernel (reg hole punched) */ + int ret = INTERNAL_SYSCALL (fadvise64_64, err, 7, fd, 0, + OFF64_HI_LO (offset), OFF64_HI_LO (len), + advice); # else int ret = INTERNAL_SYSCALL (fadvise64_64, err, 6, fd, OFF64_HI_LO (offset), OFF64_HI_LO (len),