From patchwork Sat Nov 1 09:00:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sposelenov@emcraft.com X-Patchwork-Id: 405765 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from fraxinus.osuosl.org (fraxinus.osuosl.org [140.211.166.137]) by ozlabs.org (Postfix) with ESMTP id 812E71400B6 for ; Sat, 1 Nov 2014 20:00:27 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id 594E9A257A; Sat, 1 Nov 2014 09:00:26 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HUdbWm8_Tiqy; Sat, 1 Nov 2014 09:00:24 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by fraxinus.osuosl.org (Postfix) with ESMTP id 3B256A2486; Sat, 1 Nov 2014 09:00:24 +0000 (UTC) X-Original-To: uclibc@lists.busybox.net Delivered-To: uclibc@osuosl.org Received: from silver.osuosl.org (silver.osuosl.org [140.211.166.136]) by ash.osuosl.org (Postfix) with ESMTP id 195C91CE79F for ; Sat, 1 Nov 2014 09:00:23 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by silver.osuosl.org (Postfix) with ESMTP id 131FB339F5 for ; Sat, 1 Nov 2014 09:00:23 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from silver.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id API298VT06CY for ; Sat, 1 Nov 2014 09:00:22 +0000 (UTC) X-Greylist: from auto-whitelisted by SQLgrey-1.7.6 Received: from ocean.emcraft.com (ocean.emcraft.com [213.221.7.182]) by silver.osuosl.org (Postfix) with ESMTPS id E943833942 for ; Sat, 1 Nov 2014 09:00:21 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=[IPv6:::1]) by ocean.emcraft.com with esmtp (Exim 4.76) (envelope-from ) id 1XkUXj-0003wx-RP; Sat, 01 Nov 2014 12:00:20 +0300 Message-ID: <1414832419.11706.10.camel@mehome> Subject: [PATCH 3/3] Implemented testandset() for Cortex-M3 From: Sergei Poselenov To: Bernhard Reutner-Fischer Date: Sat, 01 Nov 2014 12:00:19 +0300 In-Reply-To: <1414831960.11706.3.camel@mehome> References: <20141022141126.3e6849ec@skywanderer.emcraft.com> <723A8C88-67FA-4D54-85A5-18F2A7D3B4F0@gmail.com> <1414831960.11706.3.camel@mehome> Organization: Emcraft Systems OOO X-Mailer: Evolution 3.8.5 (3.8.5-2.fc19) Mime-Version: 1.0 Cc: uclibc@uclibc.org, Andrii X-BeenThere: uclibc@uclibc.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "Discussion and development of uClibc \(the embedded C library\)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: uclibc-bounces@uclibc.org Sender: "uClibc" commit 683a77455f2226419fe688dd2104ef1a391bb3b2 Author: Sergei Poselenov Date: Sun Oct 26 14:54:12 2014 +0400 Implemented testandset() for Cortex-M3 Signed-off-by: Sergei Poselenov diff --git a/extra/Configs/Config.arm b/extra/Configs/Config.arm index 0bb2971..5777d3b 100644 --- a/extra/Configs/Config.arm +++ b/extra/Configs/Config.arm @@ -36,3 +36,10 @@ config USE_BX Say 'y' to use BX to return from functions on your thumb-aware processor. Say 'y' if you need to use interworking. Say 'n' if not. It is safe to say 'y' even if you're not doing interworking. + +config USE_LDREXSTREX + bool "Use load-store exclusive ASM ops (not supported in SmartFusion)" + depends on COMPILE_IN_THUMB_MODE + default y + help + Say 'y' to use LDREX/STREX ASM ops. diff --git a/libpthread/linuxthreads.old/sysdeps/arm/pt-machine.h b/libpthread/linuxthreads.old/sysdeps/arm/pt-machine.h index 583eb68..93804ba 100644 --- a/libpthread/linuxthreads.old/sysdeps/arm/pt-machine.h +++ b/libpthread/linuxthreads.old/sysdeps/arm/pt-machine.h @@ -22,12 +22,50 @@ #ifndef _PT_MACHINE_H #define _PT_MACHINE_H 1 -#include +#include +#include #ifndef PT_EI # define PT_EI __extern_always_inline #endif +#if defined(__thumb__) +#if defined(__USE_LDREXSTREX__) +PT_EI long int ldrex(int *spinlock) +{ + long int ret; + __asm__ __volatile__( + "ldrex %0, [%1]\n" + : "=r"(ret) + : "r"(spinlock) : "memory"); + return ret; +} + +PT_EI long int strex(int val, int *spinlock) +{ + long int ret; + __asm__ __volatile__( + "strex %0, %1, [%2]\n" + : "=r"(ret) + : "r" (val), "r"(spinlock) : "memory"); + return ret; +} + +/* Spinlock implementation; required. */ +PT_EI long int +testandset (int *spinlock) +{ + register unsigned int ret; + + do { + ret = ldrex(spinlock); + } while (strex(1, spinlock)); + + return ret; +} + +#else /* __USE_LDREXSTREX__ */ + /* This will not work on ARM1 or ARM2 because SWP is lacking on those machines. Unfortunately we have no way to detect this at compile time; let's hope nobody tries to use one. */ @@ -37,8 +75,6 @@ PT_EI long int testandset (int *spinlock); PT_EI long int testandset (int *spinlock) { register unsigned int ret; - -#if defined(__thumb__) void *pc; __asm__ __volatile__( ".align 0\n" @@ -51,15 +87,21 @@ PT_EI long int testandset (int *spinlock) "\t.force_thumb" : "=r"(ret), "=r"(pc) : "0"(1), "r"(spinlock)); -#else + return ret; +} +#endif +#else /* __thumb__ */ + +PT_EI long int testandset (int *spinlock); +PT_EI long int testandset (int *spinlock) +{ + register unsigned int ret; __asm__ __volatile__("swp %0, %1, [%2]" : "=r"(ret) : "0"(1), "r"(spinlock)); -#endif - return ret; } - +#endif /* Get some notion of the current stack. Need not be exactly the top of the stack, just something somewhere in the current frame. */