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[4/5] UBUNTU: [Upstream] net: Add missing TST_CFG_WRITE bits around sky2_pci_write

Message ID q2qf17812d71004112334jdfd58deag89dcf3d39bc2f44c@mail.gmail.com
State Accepted
Delegated to: Andy Whitcroft
Headers show

Commit Message

Eric Miao April 12, 2010, 6:34 a.m. UTC
From bee0cda65b1e3ddae458fd9bf3f01cd4c57e9193 Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Thu, 3 Dec 2009 05:12:02 +0000
Subject: [PATCH 4/5] UBUNTU: [Upstream] net: Add missing TST_CFG_WRITE
bits around sky2_pci_write

BugLink: http://bugs.launchpad.net/bugs/537168

Add missing TST_CFG_WRITE bits around sky2_pci_write*() in Optima
setup routines.  Without the cfg-write bits, the driver may spew endless
link-up messages through qlink irq.

Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit d66f0b20b2f8eac365fadf5ca492efe4ba539446)

Signed-off-by: Eric Miao <eric.miao@canonical.com>
---
 drivers/net/sky2.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)
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Patch

diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 11aebc5..0678cc0 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -2120,7 +2120,9 @@  static void sky2_qlink_intr(struct sky2_hw *hw)

 	/* reset PHY Link Detect */
 	phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
+	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
 	sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
+	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

 	sky2_link_up(sky2);
 }
@@ -3045,6 +3047,7 @@  static void sky2_reset(struct sky2_hw *hw)
 		reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;

 		/* reset PHY Link Detect */
+		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
 		sky2_pci_write16(hw, PSM_CONFIG_REG4,
 				 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
 		sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
@@ -3062,6 +3065,7 @@  static void sky2_reset(struct sky2_hw *hw)
 			/* restore the PCIe Link Control register */
 			sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
 		}
+		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

 		/* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
 		sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));