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[2/6] x86, cpu: Add xsaveopt cpufeature

Message ID d46bd9759a01e35bc9fbc18eef2f8d0f7b6d36b0.1282613125.git.leann.ogasawara@canonical.com
State Rejected
Delegated to: Leann Ogasawara
Headers show

Commit Message

Leann Ogasawara Aug. 24, 2010, 1:58 a.m. UTC 
BugLink: https://bugs.launchpad.net/bugs/485548

Add cpu feature bit support for the XSAVEOPT instruction.

Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
LKML-Reference: <20100719230205.523204988@sbs-t61.sc.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
(backported from upstream commit 40e1d7a4ffee5cb17f5c36f4c3c4a011ab103ebe)

Signed-off-by: Leann Ogasawara <leann.ogasawara@canonical.com>
---
 arch/x86/include/asm/cpufeature.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)
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Patch

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 4681459..d431154 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -162,6 +162,7 @@ 
 #define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
 #define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */
 #define X86_FEATURE_CPB		(7*32+ 2) /* AMD Core Performance Boost */
+#define X86_FEATURE_XSAVEOPT	(7*32+4) /* "xsaveopt" Optimized Xsave */
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */