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[SRU,J:linux-bluefield,1/1] PCI: Support BAR sizes up to 8TB

Message ID 20230926110458.6329-2-bartlomiej.zolnierkiewicz@canonical.com
State New
Headers show
Series support PCI BARs larger than 128GB | expand

Commit Message

Bartlomiej Zolnierkiewicz Sept. 26, 2023, 11:04 a.m. UTC 
From: Dongdong Liu <liudongdong3@huawei.com>

BugLink: https://bugs.launchpad.net/bugs/2037403

Current kernel reports that BARs larger than 128GB, e.g., this 4TB BAR, are
disabled:

    pci 0000:01:00.0: disabling BAR 4: [mem 0x00000000-0x3ffffffffff 64bit pref] (bad alignment 0x40000000000)

Increase the maximum BAR size from 128GB to 8TB for future expansion.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20220118092117.10089-1-liudongdong3@huawei.com
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
(cherry picked from commit 3dc8a1f6f64481a8a5a669633e880f26dae0d752)
Signed-off-by: Bartlomiej Zolnierkiewicz <bartlomiej.zolnierkiewicz@canonical.com>
---
 drivers/pci/setup-bus.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 6ff0bf475bc8..369e33341728 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -994,7 +994,7 @@  static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
 {
 	struct pci_dev *dev;
 	resource_size_t min_align, align, size, size0, size1;
-	resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */
+	resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */
 	int order, max_order;
 	struct resource *b_res = find_bus_resource_of_type(bus,
 					mask | IORESOURCE_PREFETCH, type);