From patchwork Fri Apr 8 02:38:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1614677 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KZMrr3bJGz9sFy for ; Fri, 8 Apr 2022 12:39:08 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1nceWb-0003fQ-3D; Fri, 08 Apr 2022 02:39:01 +0000 Received: from mail-pg1-f174.google.com ([209.85.215.174]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1nceWW-0003Uy-2s for kernel-team@lists.ubuntu.com; Fri, 08 Apr 2022 02:38:56 +0000 Received: by mail-pg1-f174.google.com with SMTP id s21so2074403pgv.13 for ; Thu, 07 Apr 2022 19:38:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bID0G0HWA5ygJy+10rdLpGzQLKsEZZv3FtxfkYBUAfs=; b=hjv36WOriB4frZ0FFapC92URQ75rJfreQe2TXzR3YjMh64Fhq4g7twDVWuaFoe2KM+ khDably2INEgY5sXQGU1fMg5339VKGtSK+jYIpGEvbnAHmmCwubTEnPIIcxrCq6+xedc /gAE7CBbdR8XBMJEbCPBSu3vYo759Rbtz8G1jVnOYj2RUIbixz4AJrjGarhYMXFMXeTQ kXWHynehKZbvGm+tTpvyEzYOi5XcvUXVJGyehvLNq9+HHDNPZHU1Op1PVLVhh0I5vsmV ai8lrEYWYcvbVhnH+neR+Cr/kQCgzWZx0eKT199mgv08C8Ju2t4ZmoKmaTsWerK2PcV/ C3ZA== X-Gm-Message-State: AOAM53332pzjxL7Yh/q9BopPt0os4GUmDF7L8K9oanRMQYPb72Bq7CBm DXC2u1dn1QiWuW+2v22XA35b118d7KU= X-Google-Smtp-Source: ABdhPJw1kTjVpEtACHHutboPOE4XB1y5MhqaqxLJEkiBywW4LzLFGZ3My98s5OlCTz6w0kw3TrxC+w== X-Received: by 2002:a65:6409:0:b0:39c:c534:4a73 with SMTP id a9-20020a656409000000b0039cc5344a73mr5237727pgv.484.1649385533325; Thu, 07 Apr 2022 19:38:53 -0700 (PDT) Received: from localhost (114-40-204-238.dynamic-ip.hinet.net. [114.40.204.238]) by smtp.gmail.com with ESMTPSA id rm5-20020a17090b3ec500b001c7559762e9sm10036000pjb.20.2022.04.07.19.38.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Apr 2022 19:38:52 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 06/16][SRU][OEM-5.14/Jammy] cpufreq: amd-pstate: Add fast switch function for AMD P-State Date: Fri, 8 Apr 2022 10:38:28 +0800 Message-Id: <20220408023840.1379420-7-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220408023840.1379420-1-vicamo.yang@canonical.com> References: <20220408023840.1379420-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.174; envelope-from=vicamo@gmail.com; helo=mail-pg1-f174.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Huang Rui BugLink: https://bugs.launchpad.net/bugs/1956509 Introduce the fast switch function for AMD P-State on the AMD processors which support the full MSR register control. It's able to decrease the latency on interrupt context. Signed-off-by: Huang Rui Signed-off-by: Rafael J. Wysocki (cherry picked from commit 1d215f0319c20662b701692a2fafc7b3b8a58ae1) Signed-off-by: You-Sheng Yang --- drivers/cpufreq/amd-pstate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 2698ed5ec6d7..8c9c199b560e 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -183,6 +183,39 @@ static int amd_pstate_target(struct cpufreq_policy *policy, return 0; } +static void amd_pstate_adjust_perf(unsigned int cpu, + unsigned long _min_perf, + unsigned long target_perf, + unsigned long capacity) +{ + unsigned long max_perf, min_perf, des_perf, + cap_perf, lowest_nonlinear_perf; + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + cap_perf = READ_ONCE(cpudata->highest_perf); + lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); + + des_perf = cap_perf; + if (target_perf < capacity) + des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity); + + min_perf = READ_ONCE(cpudata->highest_perf); + if (_min_perf < capacity) + min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity); + + if (min_perf < lowest_nonlinear_perf) + min_perf = lowest_nonlinear_perf; + + max_perf = cap_perf; + if (max_perf < min_perf) + max_perf = min_perf; + + des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); + + amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true); +} + static int amd_get_min_freq(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; @@ -299,6 +332,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; + policy->fast_switch_possible = true; + /* Initial processor data capability frequencies */ cpudata->max_freq = max_freq; cpudata->min_freq = min_freq; @@ -329,6 +364,7 @@ static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, .target = amd_pstate_target, + .adjust_perf = amd_pstate_adjust_perf, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, .name = "amd-pstate",