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[2001:56a:78ed:fb00:55b6:539c:aab3:b032]) by smtp.gmail.com with ESMTPSA id l1sm2656275pgn.35.2022.01.06.13.08.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 13:08:39 -0800 (PST) From: Alex Hung To: kernel-team@lists.ubuntu.com Subject: [PATCH 1/1][SRU][J] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs Date: Thu, 6 Jan 2022 14:08:37 -0700 Message-Id: <20220106210837.1600983-2-alex.hung@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220106210837.1600983-1-alex.hung@canonical.com> References: <20220106210837.1600983-1-alex.hung@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Deepak Sharma BugLink: https://bugs.launchpad.net/bugs/1941893 All Zen or newer CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause drop in performance for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly. Signed-off-by: Deepak Sharma Acked-by: Thomas Gleixner Signed-off-by: Rafael J. Wysocki (cherry picked from commit a8fb40966f19ff81520d9ccf8f7e2b95201368b8) Signed-off-by: Alex Hung --- arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index 7de599eba7f0..7945eae5b315 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, */ flags->bm_control = 0; } + if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17) { + /* + * For all AMD Zen or newer CPUs that support C3, caches + * should not be flushed by software while entering C3 + * type state. Set bm->check to 1 so that kernel doesn't + * need to execute cache flush operation. + */ + flags->bm_check = 1; + /* + * In current AMD C state implementation ARB_DIS is no longer + * used. So set bm_control to zero to indicate ARB_DIS is not + * required while entering C3 type state. + */ + flags->bm_control = 0; + } } EXPORT_SYMBOL(acpi_processor_power_init_bm_check);