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[111.240.133.170]) by smtp.gmail.com with ESMTPSA id v15sm17708541pfu.195.2021.11.24.02.23.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Nov 2021 02:23:32 -0800 (PST) From: Chris Chiu To: kernel-team@lists.ubuntu.com Subject: [PATCH 12/12][SRU][U/OEM-5.14] drm/i915/tc: Fix system hang on ADL-P during TypeC PHY disconnect Date: Wed, 24 Nov 2021 18:23:15 +0800 Message-Id: <20211124102315.447617-13-chris.chiu@canonical.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211124102315.447617-1-chris.chiu@canonical.com> References: <20211124102315.447617-1-chris.chiu@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Imre Deak BugLink: https://bugs.launchpad.net/bugs/1952041 The PHY ownership release->AUX PW disable steps during a modeset disable->PHY disconnect sequence can hang the system if the PHY disconnect happens after disabling the PHY's PLL. The spec doesn't require a specific order for these two steps, so this issue is still being root caused by HW/FW teams. Until that is found, let's make sure the disconnect happens before the PLL is disabled, and do this on all platforms for consistency. v2: Add a TODO comment to remove the w/a once the issue is root caused/fixed. (Jose) Cc: José Roberto de Souza Signed-off-by: Imre Deak Reviewed-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20210929132833.2253961-7-imre.deak@intel.com (cherry picked from commit b58a88682093b3438dad66f2c3d3a4d0a20ee1e8) Signed-off-by: Chris Chiu --- drivers/gpu/drm/i915/display/intel_tc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 4a14db604cba..40faa18947c9 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -834,6 +834,14 @@ void intel_tc_port_put_link(struct intel_digital_port *dig_port) intel_tc_port_lock(dig_port); --dig_port->tc_link_refcount; intel_tc_port_unlock(dig_port); + + /* + * Disconnecting the PHY after the PHY's PLL gets disabled may + * hang the system on ADL-P, so disconnect the PHY here synchronously. + * TODO: remove this once the root cause of the ordering requirement + * is found/fixed. + */ + intel_tc_port_flush_work(dig_port); } static bool