diff mbox series

[SRU,H/Unstable,1/2] drm/i915/display: Do not allow DC3CO if PSR SF is enabled

Message ID 20210506034817.9830-2-hui.wang@canonical.com
State New
Headers show
Series Display abnormal on the TGL+4k panel machines | expand

Commit Message

Hui Wang May 6, 2021, 3:48 a.m. UTC 
From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

BugLink: https://bugs.launchpad.net/bugs/1922885

Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exit mechanism
has an issue with using of Selective Fecth and PSR2 manual tracking.
And as some GEN12+ platforms (RKL, ADL-S) don't support PSR2 HW tracking,
Selective Fetch will be enabled by default on that platforms.
Therefore if the system enables PSR Selective Fetch / PSR manual tracking,
it does not allow DC3CO dc state, in that case.

When this DC3CO exit issue is addressed while PSR Selective Fetch is
enabled, this restriction should be removed.

v2: Address Jose's review comment.
  - Fix typo
  - Move check routine of DC3CO ability to
    tgl_dc3co_exitline_compute_config()
v3: Change the check routine of enablement of psr2 sel fetch. (Jose)

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210222213006.1609085-1-gwan-gyeong.mun@intel.com
(cherry picked from commit 62c211bb9e1bee0083d8061ce0012f538ac754c3)
Signed-off-by: Hui Wang <hui.wang@canonical.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++
 1 file changed, 7 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f789b977264d..f6a5751276ba 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -654,6 +654,13 @@  tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u32 exit_scanlines;
 
+	/*
+	 * DMC's DC3CO exit mechanism has an issue with Selective Fecth
+	 * TODO: when the issue is addressed, this restriction should be removed.
+	 */
+	if (crtc_state->enable_psr2_sel_fetch)
+		return;
+
 	if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
 		return;