diff mbox series

[2/2,SRU,G] drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock

Message ID 20200910052736.314874-3-shane.lin@canonical.com
State New
Headers show
Series Support WD19TB external output on TGL platform | expand

Commit Message

Hsuan-Yu Lin Sept. 10, 2020, 5:27 a.m. UTC
From: Imre Deak <imre.deak@intel.com>

BugLink: https://bugs.launchpad.net/bugs/1886165

When the reference clock is 38.4MHz, using the current TBT PLL
fractional divider value results in a slightly off TBT link frequency.
This causes an endless loop of link training success followed by a bad
link signaling and retraining at least on a Dell WD19TB TBT dock.  The
workaround provided by the HW team is to divide the fractional divider
value by two. This fixed the link training problem on the ThinkPad dock.

The same workaround is needed on some EHL platforms and for combo PHY
PLLs, these will be addressed in a follow-up.

Bspec: 49204

References: HSDES#22010772725
References: HSDES#14011861142
Reported-and-tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200629185848.20550-1-imre.deak@intel.com
(cherry picked from commit 09eac8277262bea10a52159f90dcb55beffe0714)
Signed-off-by: Hsuan-Yu Lin <shane.lin@canonical.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b45185b80bec..720aff8b9313 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2934,6 +2934,15 @@  static const struct skl_wrpll_params tgl_tbt_pll_19_2MHz_values = {
 static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
 	.dco_integer = 0x43, .dco_fraction = 0x4000,
 	/* the following params are unused */
+};
+
+/*
+ * Display WA #22010492432: tgl
+ * Divide the nominal .dco_fraction value by 2.
+ */
+static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = {
+	.dco_integer = 0x54, .dco_fraction = 0x1800,
+	/* the following params are unused */
 	.pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
 };
 
@@ -2970,12 +2979,14 @@  static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
 			MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
 			/* fall-through */
 		case 19200:
-		case 38400:
 			*pll_params = tgl_tbt_pll_19_2MHz_values;
 			break;
 		case 24000:
 			*pll_params = tgl_tbt_pll_24MHz_values;
 			break;
+		case 38400:
+			*pll_params = tgl_tbt_pll_38_4MHz_values;
+			break;
 		}
 	} else {
 		switch (dev_priv->dpll.ref_clks.nssc) {