diff mbox series

[SRU,B,v2,1/1] s390/cpum_cf, perf: change DFLT_CCERROR counter name

Message ID 20200828071937.40697-2-frank.heimes@canonical.com
State New
Headers show
Series kernel: s390/cpum_cf, perf: change DFLT_CCERROR counter name (LP: 1891454) | expand

Commit Message

Frank Heimes Aug. 28, 2020, 7:19 a.m. UTC
From: Thomas Richter <tmricht@linux.ibm.com>

BugLink: https://bugs.launchpad.net/bugs/1891454

Add CPU measurement counter facility event description for IBM z15.

Fixes: d68d5d51dc89 ("s390/cpum_cf: Add new extended counters for IBM z15")
Fixes: e7950166e402 ("perf vendor events s390: Add new deflate counters for IBM z15")
Cc: stable@vger.kernel.org # v5.7
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Reviewed-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
(backported from commit 3d3af181d370069861a3be94608464e2ff3682e2)
Signed-off-by: Frank Heimes <frank.heimes@canonical.com>
---
 arch/s390/kernel/perf_cpum_cf_events.c | 123 ++++++++++++++++++++++++-
 1 file changed, 122 insertions(+), 1 deletion(-)

Comments

Kleber Souza Aug. 28, 2020, 9:19 a.m. UTC | #1
On 28.08.20 09:19, frank.heimes@canonical.com wrote:
> From: Thomas Richter <tmricht@linux.ibm.com>
> 
> BugLink: https://bugs.launchpad.net/bugs/1891454
> 
> Add CPU measurement counter facility event description for IBM z15.
> 
> Fixes: d68d5d51dc89 ("s390/cpum_cf: Add new extended counters for IBM z15")
> Fixes: e7950166e402 ("perf vendor events s390: Add new deflate counters for IBM z15")
> Cc: stable@vger.kernel.org # v5.7
> Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
> Reviewed-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
> Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
> (backported from commit 3d3af181d370069861a3be94608464e2ff3682e2)
> Signed-off-by: Frank Heimes <frank.heimes@canonical.com>

Hi Frank,

The provenance block and the subject is from 3d3af181d370 "s390/cpum_cf,perf: change
DFLT_CCERROR counter name", but the commit message and the patch content is from
d68d5d51dc89 "s390/cpum_cf: Add new extended counters for IBM z15".

Can you please re-submit with the correct subject/commit message?


Kleber


> ---
>  arch/s390/kernel/perf_cpum_cf_events.c | 123 ++++++++++++++++++++++++-
>  1 file changed, 122 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/s390/kernel/perf_cpum_cf_events.c b/arch/s390/kernel/perf_cpum_cf_events.c
> index 1bafe96cc91f..894d99f5fce1 100644
> --- a/arch/s390/kernel/perf_cpum_cf_events.c
> +++ b/arch/s390/kernel/perf_cpum_cf_events.c
> @@ -237,6 +237,64 @@ CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
>  CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
>  CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
>  
> +CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
> +CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
> +CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
> +CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083);
> +CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085);
> +CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086);
> +CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088);
> +CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089);
> +CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a);
> +CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b);
> +CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c);
> +CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d);
> +CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
> +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
> +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
> +CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
> +CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1);
> +CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2);
> +CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8);
> +CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3);
> +CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4);
> +CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5);
> +CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7);
> +CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc);
> +CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108);
> +CPUMF_EVENT_ATTR(cf_z15, DFLT_CCFINISH, 0x00109);
> +CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
> +CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
> +
>  static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
>  	CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
>  	CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
> @@ -515,6 +573,67 @@ static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
>  	NULL,
>  };
>  
> +static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = {
> +	CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES),
> +	CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY),
> +	CPUMF_EVENT_PTR(cf_z15, TX_C_TEND),
> +	CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND),
> +	CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES),
> +	CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS),
> +	CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS),
> +	CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS),
> +	CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS),
> +	CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT),
> +	CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL),
> +	CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL),
> +	CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS),
> +	CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES),
> +	CPUMF_EVENT_PTR(cf_z15, DFLT_CC),
> +	CPUMF_EVENT_PTR(cf_z15, DFLT_CCFINISH),
> +	CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
> +	CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
> +	NULL,
> +};
> +
>  /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
>  
>  static struct attribute_group cpumcf_pmu_events_group = {
> @@ -623,9 +742,11 @@ __init const struct attribute_group **cpumf_cf_event_group(void)
>  		break;
>  	case 0x3906:
>  	case 0x3907:
> +		model = cpumcf_z14_pmu_event_attr;
> +		break;
>  	case 0x8561:
>  	case 0x8562:
> -		model = cpumcf_z14_pmu_event_attr;
> +		model = cpumcf_z15_pmu_event_attr;
>  		break;
>  	default:
>  		model = none;
>
Frank Heimes Aug. 28, 2020, 11:07 a.m. UTC | #2
Hi Kleber,
I guess it was not a good idea to just change the already generated patch
files manually to create and submit the v2.
The description and content was ok, but not subject and nor provenance.

Anyway, I just re-ran the entire process from scratch (but for bionic only)
incl. git format-patch to not miss anything.
It's submitted as v3 here:
https://lists.ubuntu.com/archives/kernel-team/2020-August/thread.html#113079

It's a bit confusing, because the counter name gets changed with the
patch/backport for focal (because it already exists in focal), but it gets
added to bionic, but there already with the correct name. Therefore the two
backports are based on different upstream commits.

I guess in future it would be better if I create two different LP bugs in
such a case (with then two separate SRU submissions) ...

Sorry, Frank


On Fri, Aug 28, 2020 at 11:19 AM Kleber Souza <kleber.souza@canonical.com>
wrote:

> On 28.08.20 09:19, frank.heimes@canonical.com wrote:
> > From: Thomas Richter <tmricht@linux.ibm.com>
> >
> > BugLink: https://bugs.launchpad.net/bugs/1891454
> >
> > Add CPU measurement counter facility event description for IBM z15.
> >
> > Fixes: d68d5d51dc89 ("s390/cpum_cf: Add new extended counters for IBM
> z15")
> > Fixes: e7950166e402 ("perf vendor events s390: Add new deflate counters
> for IBM z15")
> > Cc: stable@vger.kernel.org # v5.7
> > Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
> > Reviewed-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
> > Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
> > (backported from commit 3d3af181d370069861a3be94608464e2ff3682e2)
> > Signed-off-by: Frank Heimes <frank.heimes@canonical.com>
>
> Hi Frank,
>
> The provenance block and the subject is from 3d3af181d370
> "s390/cpum_cf,perf: change
> DFLT_CCERROR counter name", but the commit message and the patch content
> is from
> d68d5d51dc89 "s390/cpum_cf: Add new extended counters for IBM z15".
>
> Can you please re-submit with the correct subject/commit message?
>
>
> Kleber
>
>
> > ---
> >  arch/s390/kernel/perf_cpum_cf_events.c | 123 ++++++++++++++++++++++++-
> >  1 file changed, 122 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/s390/kernel/perf_cpum_cf_events.c
> b/arch/s390/kernel/perf_cpum_cf_events.c
> > index 1bafe96cc91f..894d99f5fce1 100644
> > --- a/arch/s390/kernel/perf_cpum_cf_events.c
> > +++ b/arch/s390/kernel/perf_cpum_cf_events.c
> > @@ -237,6 +237,64 @@ CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL,
> 0x00f5);
> >  CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
> >  CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
> >
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
> > +CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
> > +CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
> > +CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083);
> > +CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085);
> > +CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086);
> > +CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088);
> > +CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089);
> > +CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a);
> > +CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b);
> > +CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c);
> > +CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d);
> > +CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
> > +CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
> > +CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
> > +CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
> > +CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1);
> > +CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2);
> > +CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8);
> > +CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3);
> > +CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4);
> > +CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5);
> > +CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7);
> > +CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc);
> > +CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108);
> > +CPUMF_EVENT_ATTR(cf_z15, DFLT_CCFINISH, 0x00109);
> > +CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
> > +CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
> > +
> >  static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
> >       CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
> >       CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
> > @@ -515,6 +573,67 @@ static struct attribute
> *cpumcf_z14_pmu_event_attr[] __initdata = {
> >       NULL,
> >  };
> >
> > +static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = {
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES),
> > +     CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY),
> > +     CPUMF_EVENT_PTR(cf_z15, TX_C_TEND),
> > +     CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND),
> > +     CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES),
> > +     CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS),
> > +     CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS),
> > +     CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS),
> > +     CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS),
> > +     CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT),
> > +     CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL),
> > +     CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL),
> > +     CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS),
> > +     CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES),
> > +     CPUMF_EVENT_PTR(cf_z15, DFLT_CC),
> > +     CPUMF_EVENT_PTR(cf_z15, DFLT_CCFINISH),
> > +     CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
> > +     CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
> > +     NULL,
> > +};
> > +
> >  /* END: CPUM_CF COUNTER DEFINITIONS
> ===================================== */
> >
> >  static struct attribute_group cpumcf_pmu_events_group = {
> > @@ -623,9 +742,11 @@ __init const struct attribute_group
> **cpumf_cf_event_group(void)
> >               break;
> >       case 0x3906:
> >       case 0x3907:
> > +             model = cpumcf_z14_pmu_event_attr;
> > +             break;
> >       case 0x8561:
> >       case 0x8562:
> > -             model = cpumcf_z14_pmu_event_attr;
> > +             model = cpumcf_z15_pmu_event_attr;
> >               break;
> >       default:
> >               model = none;
> >
>
>
diff mbox series

Patch

diff --git a/arch/s390/kernel/perf_cpum_cf_events.c b/arch/s390/kernel/perf_cpum_cf_events.c
index 1bafe96cc91f..894d99f5fce1 100644
--- a/arch/s390/kernel/perf_cpum_cf_events.c
+++ b/arch/s390/kernel/perf_cpum_cf_events.c
@@ -237,6 +237,64 @@  CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
 
+CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
+CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
+CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
+CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083);
+CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084);
+CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085);
+CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086);
+CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087);
+CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088);
+CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089);
+CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a);
+CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b);
+CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c);
+CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d);
+CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f);
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
+CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
+CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
+CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
+CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
+CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
+CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1);
+CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2);
+CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8);
+CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3);
+CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4);
+CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5);
+CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7);
+CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc);
+CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108);
+CPUMF_EVENT_ATTR(cf_z15, DFLT_CCFINISH, 0x00109);
+CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
+CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
+
 static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
 	CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
 	CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
@@ -515,6 +573,67 @@  static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
 	NULL,
 };
 
+static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = {
+	CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES),
+	CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES),
+	CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY),
+	CPUMF_EVENT_PTR(cf_z15, TX_C_TEND),
+	CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND),
+	CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
+	CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES),
+	CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS),
+	CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS),
+	CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS),
+	CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS),
+	CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT),
+	CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL),
+	CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL),
+	CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS),
+	CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES),
+	CPUMF_EVENT_PTR(cf_z15, DFLT_CC),
+	CPUMF_EVENT_PTR(cf_z15, DFLT_CCFINISH),
+	CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
+	CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
+	NULL,
+};
+
 /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
 
 static struct attribute_group cpumcf_pmu_events_group = {
@@ -623,9 +742,11 @@  __init const struct attribute_group **cpumf_cf_event_group(void)
 		break;
 	case 0x3906:
 	case 0x3907:
+		model = cpumcf_z14_pmu_event_attr;
+		break;
 	case 0x8561:
 	case 0x8562:
-		model = cpumcf_z14_pmu_event_attr;
+		model = cpumcf_z15_pmu_event_attr;
 		break;
 	default:
 		model = none;