From patchwork Fri Aug 14 06:57:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344663 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ5k4j7yz9sTH; Fri, 14 Aug 2020 16:58:18 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TfJ-0007j8-V1; Fri, 14 Aug 2020 06:58:14 +0000 Received: from mail-pg1-f195.google.com ([209.85.215.195]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6TfE-0007de-0b for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:08 +0000 Received: by mail-pg1-f195.google.com with SMTP id h12so4082037pgm.7 for ; Thu, 13 Aug 2020 23:58:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CFzlwlxdZeHeA893xkc/StWVGHGSHleEmaWvY7Wvw30=; b=jXR4XHN7Sohni8yyi36AUE6cnqFiKCmkoU/Jke3ue0ammQlrSG+zqCCMrskPCRrEpU rthjQCP3S09chgiwVBfEMjQw/q1sUI6PD57PBcdUQuy+dc0i2R02Z0tCIr79g0xEZOqo YRu3FCZwmeO9GmC/lnbKKlC7pSqAciPD1q0UBxj+Z/dfVls72T6+DCIBfpSfjMQTkeM6 vz+MV2ghVbC7EnsY351Us3F5IoYHHdF0OeS7mPeWyx6OLtwOD7UiNBaHiouLNRKGYiW/ 5Jjscj+kgHgPQ8tC+X7IIYDamtAsqzowwbz4l5DBHfRvGBFjNiAngCNECyBy41kq9dmD LcbA== X-Gm-Message-State: AOAM532UMT6TBDT3INNk1Z6GEKElRkMmib6NpUjGlbe/13CZarvUXTt0 ykByj9/hVID2kxHXATESuZs9wkC1pruyqA== X-Google-Smtp-Source: ABdhPJwQGZhGCxbyyoYGVeZnM/EYon6mMc3OxubK+AOa8bjssL/E5ZvsewHnsFv7WcgMhUUAlXN8DA== X-Received: by 2002:aa7:960f:: with SMTP id q15mr882700pfg.79.1597388285794; Thu, 13 Aug 2020 23:58:05 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id b63sm7958990pfg.43.2020.08.13.23.58.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:05 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 08/31][SRU][OEM-5.6] drm/i915: s/init_cdclk/init_cdclk_hw/ Date: Fri, 14 Aug 2020 14:57:17 +0800 Message-Id: <20200814065740.276039-9-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.195; envelope-from=vicamo@gmail.com; helo=mail-pg1-f195.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Give the cdclk init/uninit functions a _hw suffix to make it clear they are about initializing the actual hardware. I'll be wanting to to add a intel_cdclk_init() which is purely initializing software structures. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-12-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak (cherry picked from commit ed645eee131c89041fde1b10c76396057588bdbd) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_cdclk.c | 24 +++++++++---------- drivers/gpu/drm/i915/display/intel_cdclk.h | 4 ++-- .../drm/i915/display/intel_display_power.c | 16 ++++++------- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 2a4540d426fd..780721af61a0 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1122,7 +1122,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) dev_priv->cdclk.hw.vco = -1; } -static void skl_init_cdclk(struct drm_i915_private *dev_priv) +static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) { struct intel_cdclk_config cdclk_config; @@ -1151,7 +1151,7 @@ static void skl_init_cdclk(struct drm_i915_private *dev_priv) skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } -static void skl_uninit_cdclk(struct drm_i915_private *dev_priv) +static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) { struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; @@ -1693,7 +1693,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) dev_priv->cdclk.hw.vco = -1; } -static void bxt_init_cdclk(struct drm_i915_private *dev_priv) +static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) { struct intel_cdclk_config cdclk_config; @@ -1718,7 +1718,7 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv) bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } -static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) +static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) { struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; @@ -1731,7 +1731,7 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) } /** - * intel_cdclk_init - Initialize CDCLK + * intel_cdclk_init_hw - Initialize CDCLK hardware * @i915: i915 device * * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and @@ -1739,27 +1739,27 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) * during the display core initialization sequence, after which the DMC will * take care of turning CDCLK off/on as needed. */ -void intel_cdclk_init(struct drm_i915_private *i915) +void intel_cdclk_init_hw(struct drm_i915_private *i915) { if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10) - bxt_init_cdclk(i915); + bxt_cdclk_init_hw(i915); else if (IS_GEN9_BC(i915)) - skl_init_cdclk(i915); + skl_cdclk_init_hw(i915); } /** - * intel_cdclk_uninit - Uninitialize CDCLK + * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware * @i915: i915 device * * Uninitialize CDCLK. This is done only during the display core * uninitialization sequence. */ -void intel_cdclk_uninit(struct drm_i915_private *i915) +void intel_cdclk_uninit_hw(struct drm_i915_private *i915) { if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915)) - bxt_uninit_cdclk(i915); + bxt_cdclk_uninit_hw(i915); else if (IS_GEN9_BC(i915)) - skl_uninit_cdclk(i915); + skl_cdclk_uninit_hw(i915); } /** diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index a3fb7b8e8d31..4b965db07720 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -23,8 +23,8 @@ struct intel_cdclk_vals { }; int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); -void intel_cdclk_init(struct drm_i915_private *i915); -void intel_cdclk_uninit(struct drm_i915_private *i915); +void intel_cdclk_init_hw(struct drm_i915_private *i915); +void intel_cdclk_uninit_hw(struct drm_i915_private *i915); void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); void intel_update_max_cdclk(struct drm_i915_private *dev_priv); void intel_update_cdclk(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index dec2c94ee51b..4f79065669d7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4827,7 +4827,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); gen9_dbuf_enable(dev_priv); @@ -4844,7 +4844,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* The spec doesn't call for removing the reset handshake flag */ /* disable PG1 and Misc I/O */ @@ -4888,7 +4888,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume mutex_unlock(&power_domains->lock); - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); gen9_dbuf_enable(dev_priv); @@ -4905,7 +4905,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* The spec doesn't call for removing the reset handshake flag */ @@ -4947,7 +4947,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume mutex_unlock(&power_domains->lock); /* 5. Enable CD clock */ - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); /* 6. Enable DBUF */ gen9_dbuf_enable(dev_priv); @@ -4969,7 +4969,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); /* 3. Disable CD clock */ - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* * 4. Disable Power Well 1 (PG1). @@ -5074,7 +5074,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); /* 4. Enable CDCLK. */ - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); /* 5. Enable DBUF. */ icl_dbuf_enable(dev_priv); @@ -5103,7 +5103,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) icl_dbuf_disable(dev_priv); /* 3. Disable CD clock */ - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* * 4. Disable Power Well 1 (PG1).