diff mbox series

[07/31,SRU,OEM-5.6] drm/i915: swap() the entire cdclk state

Message ID 20200814065740.276039-8-vicamo.yang@canonical.com
State New
Headers show
Series Add TGL+ SAGV display support | expand

Commit Message

You-Sheng Yang Aug. 14, 2020, 6:57 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

BugLink: https://bugs.launchpad.net/bugs/1891451

To make life less confusing let's swap() the entire cdclk state
rather than swapping some parts, copying other parts, and leaving
the rest just as is.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-11-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
(cherry picked from commit 4c029c499fb446d97b85509c151f8564dfe1dcc3)
Signed-off-by: You-Sheng Yang <vicamo.yang@canonical.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++---------------
 1 file changed, 3 insertions(+), 15 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index e219b2fb986c..2a4540d426fd 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1847,19 +1847,7 @@  void intel_cdclk_swap_state(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 
-	/* FIXME maybe swap() these too */
-	memcpy(dev_priv->cdclk_state.min_cdclk,
-	       state->cdclk_state.min_cdclk,
-	       sizeof(state->cdclk_state.min_cdclk));
-	memcpy(dev_priv->cdclk_state.min_voltage_level,
-	       state->cdclk_state.min_voltage_level,
-	       sizeof(state->cdclk_state.min_voltage_level));
-
-	dev_priv->cdclk_state.force_min_cdclk =
-		state->cdclk_state.force_min_cdclk;
-
-	swap(state->cdclk_state.logical, dev_priv->cdclk_state.logical);
-	swap(state->cdclk_state.actual, dev_priv->cdclk_state.actual);
+	swap(state->cdclk_state, dev_priv->cdclk_state);
 }
 
 void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
@@ -1915,7 +1903,7 @@  intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 	/* called after intel_cdclk_swap_state()! */
 	const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
 	const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
-	enum pipe pipe = old_cdclk_state->pipe; /* not swapped */
+	enum pipe pipe = new_cdclk_state->pipe;
 
 	if (pipe == INVALID_PIPE ||
 	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk)
@@ -1936,7 +1924,7 @@  intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 	/* called after intel_cdclk_swap_state()! */
 	const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
 	const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
-	enum pipe pipe = old_cdclk_state->pipe; /* not swapped */
+	enum pipe pipe = new_cdclk_state->pipe;
 
 	if (pipe != INVALID_PIPE &&
 	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk)