From patchwork Fri Aug 14 06:57:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344657 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ5L06YRz9sTT; Fri, 14 Aug 2020 16:57:57 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6Tf0-0007W9-Km; Fri, 14 Aug 2020 06:57:54 +0000 Received: from mail-pj1-f67.google.com ([209.85.216.67]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6Tey-0007Up-8l for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:57:52 +0000 Received: by mail-pj1-f67.google.com with SMTP id l60so3967227pjb.3 for ; Thu, 13 Aug 2020 23:57:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SYKRgbsvH+L3MmbHPlJF2g0KUij1+p3QoPG+D8RVP8k=; b=BxsSdOhqQWfvgeVqJ66AGIFLv4KYRtgbMwzvLyRdKu335gjvHy6aLrbd1pNUkfapXB 2oGB6DKZtevohjgkTbXJMH1In5WrP1Gf6SmBZ9r166BmlZArGj3UIObAnYq/NbNmjG3b jSFoF20bkxsYcOMwDLB8iAepl8DbUlmOgFLv1LQijUT5i0//hWQf/4DAcyfeY8gtr7ue pxoctp2hJ4ZlIotpMtCzehoFKcbdYs+fDS+Cu4+AyTM/ACxawbVer808e8xeNKQX3qX1 2Ll2PS87GER9rm+2YzEAZtuA+PwBEhGMpItJ0g+UzSd5d5vVYMh3ihpyLZy9S+Byxzaj 2bGQ== X-Gm-Message-State: AOAM530BD8OQytwG9uGmYcS2EnF+bVksbY9pRZIS9wGrUBB7ro6LJZ3m teT8lA8ZS2tZh80pdIRYaz9iaavCOTLzfg== X-Google-Smtp-Source: ABdhPJx6/G7wB7SDheSSsKcKldvqZOGBI3YX8Pc77+O15cLlCzPXwVEwQo+SMfVtxKqWEInOXfkhsA== X-Received: by 2002:a17:90b:470a:: with SMTP id jc10mr1142526pjb.141.1597388269738; Thu, 13 Aug 2020 23:57:49 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id p1sm7215155pjp.10.2020.08.13.23.57.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:57:48 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 02/31][SRU][OEM-5.6] drm/i915: Collect more cdclk state under the same roof Date: Fri, 14 Aug 2020 14:57:11 +0800 Message-Id: <20200814065740.276039-3-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.67; envelope-from=vicamo@gmail.com; helo=mail-pj1-f67.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Move the min_cdclk[] and min_voltage_level[] arrays under the rest of the cdclk state. And while at it provide a simple helper (intel_cdclk_clear_state()) to clear the state during the ww_mutex backoff dance. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-6-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza (cherry picked from commit b4db3a8c689ba5f5ced764ab1377ad6411003b0b) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_atomic.c | 9 ++--- drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++++++++++++------- drivers/gpu/drm/i915/display/intel_cdclk.h | 1 + drivers/gpu/drm/i915/display/intel_display.c | 8 ++-- .../drm/i915/display/intel_display_types.h | 10 +++-- drivers/gpu/drm/i915/i915_drv.h | 9 +++-- 6 files changed, 46 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index c362eecdd414..1269f63ea006 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -35,6 +35,7 @@ #include #include "intel_atomic.h" +#include "intel_cdclk.h" #include "intel_display_types.h" #include "intel_hdcp.h" #include "intel_psr.h" @@ -497,15 +498,13 @@ intel_atomic_state_alloc(struct drm_device *dev) void intel_atomic_state_clear(struct drm_atomic_state *s) { struct intel_atomic_state *state = to_intel_atomic_state(s); + drm_atomic_state_default_clear(&state->base); + state->dpll_set = state->modeset = false; state->global_state_changed = false; state->active_pipes = 0; - memset(&state->min_cdclk, 0, sizeof(state->min_cdclk)); - memset(&state->min_voltage_level, 0, sizeof(state->min_voltage_level)); - memset(&state->cdclk.logical, 0, sizeof(state->cdclk.logical)); - memset(&state->cdclk.actual, 0, sizeof(state->cdclk.actual)); - state->cdclk.pipe = INVALID_PIPE; + intel_cdclk_clear_state(state); } struct intel_crtc_state * diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index b2c8a027b442..ca0510e74516 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1815,6 +1815,18 @@ static bool intel_cdclk_changed(const struct intel_cdclk_state *a, a->voltage_level != b->voltage_level; } +/** + * intel_cdclk_clear_state - clear the cdclk state + * @state: atomic state + * + * Clear the cdclk state for ww_mutex backoff. + */ +void intel_cdclk_clear_state(struct intel_atomic_state *state) +{ + memset(&state->cdclk, 0, sizeof(state->cdclk)); + state->cdclk.pipe = INVALID_PIPE; +} + /** * intel_cdclk_swap_state - make atomic CDCLK configuration effective * @state: atomic state @@ -1832,10 +1844,10 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state) struct drm_i915_private *dev_priv = to_i915(state->base.dev); /* FIXME maybe swap() these too */ - memcpy(dev_priv->min_cdclk, state->min_cdclk, - sizeof(state->min_cdclk)); - memcpy(dev_priv->min_voltage_level, state->min_voltage_level, - sizeof(state->min_voltage_level)); + memcpy(dev_priv->cdclk.min_cdclk, state->cdclk.min_cdclk, + sizeof(state->cdclk.min_cdclk)); + memcpy(dev_priv->cdclk.min_voltage_level, state->cdclk.min_voltage_level, + sizeof(state->cdclk.min_voltage_level)); dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk; @@ -2060,10 +2072,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) if (min_cdclk < 0) return min_cdclk; - if (state->min_cdclk[i] == min_cdclk) + if (state->cdclk.min_cdclk[i] == min_cdclk) continue; - state->min_cdclk[i] = min_cdclk; + state->cdclk.min_cdclk[i] = min_cdclk; ret = intel_atomic_lock_global_state(state); if (ret) @@ -2072,7 +2084,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) min_cdclk = state->cdclk.force_min_cdclk; for_each_pipe(dev_priv, pipe) - min_cdclk = max(state->min_cdclk[pipe], min_cdclk); + min_cdclk = max(state->cdclk.min_cdclk[pipe], min_cdclk); return min_cdclk; } @@ -2107,10 +2119,10 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) else min_voltage_level = 0; - if (state->min_voltage_level[i] == min_voltage_level) + if (state->cdclk.min_voltage_level[i] == min_voltage_level) continue; - state->min_voltage_level[i] = min_voltage_level; + state->cdclk.min_voltage_level[i] = min_voltage_level; ret = intel_atomic_lock_global_state(state); if (ret) @@ -2119,7 +2131,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) min_voltage_level = 0; for_each_pipe(dev_priv, pipe) - min_voltage_level = max(state->min_voltage_level[pipe], + min_voltage_level = max(state->cdclk.min_voltage_level[pipe], min_voltage_level); return min_voltage_level; @@ -2353,10 +2365,10 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) enum pipe pipe; int ret; - memcpy(state->min_cdclk, dev_priv->min_cdclk, - sizeof(state->min_cdclk)); - memcpy(state->min_voltage_level, dev_priv->min_voltage_level, - sizeof(state->min_voltage_level)); + memcpy(state->cdclk.min_cdclk, dev_priv->cdclk.min_cdclk, + sizeof(state->cdclk.min_cdclk)); + memcpy(state->cdclk.min_voltage_level, dev_priv->cdclk.min_voltage_level, + sizeof(state->cdclk.min_voltage_level)); /* keep the current setting */ if (!state->cdclk.force_min_cdclk_changed) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index cf71394cc79c..3f3773c582ae 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -31,6 +31,7 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv); void intel_update_rawclk(struct drm_i915_private *dev_priv); bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, const struct intel_cdclk_state *b); +void intel_cdclk_clear_state(struct intel_atomic_state *state); void intel_cdclk_swap_state(struct intel_atomic_state *state); void intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 11f93d11079f..f405f9c1512d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7565,8 +7565,8 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, crtc->enabled_power_domains = 0; dev_priv->active_pipes &= ~BIT(pipe); - dev_priv->min_cdclk[pipe] = 0; - dev_priv->min_voltage_level[pipe] = 0; + dev_priv->cdclk.min_cdclk[pipe] = 0; + dev_priv->cdclk.min_voltage_level[pipe] = 0; bw_state->data_rate[pipe] = 0; bw_state->num_active_planes[pipe] = 0; @@ -18313,8 +18313,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) min_cdclk = 0; } - dev_priv->min_cdclk[crtc->pipe] = min_cdclk; - dev_priv->min_voltage_level[crtc->pipe] = + dev_priv->cdclk.min_cdclk[crtc->pipe] = min_cdclk; + dev_priv->cdclk.min_voltage_level[crtc->pipe] = crtc_state->min_voltage_level; intel_bw_crtc_update(bw_state, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 7000adce712d..d7a5f2e5fd14 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -479,6 +479,12 @@ struct intel_atomic_state { int force_min_cdclk; bool force_min_cdclk_changed; + + /* minimum acceptable cdclk for each pipe */ + int min_cdclk[I915_MAX_PIPES]; + /* minimum acceptable voltage level for each pipe */ + u8 min_voltage_level[I915_MAX_PIPES]; + /* pipe to which cd2x update is synchronized */ enum pipe pipe; } cdclk; @@ -496,10 +502,6 @@ struct intel_atomic_state { u8 active_pipe_changes; u8 active_pipes; - /* minimum acceptable cdclk for each pipe */ - int min_cdclk[I915_MAX_PIPES]; - /* minimum acceptable voltage level for each pipe */ - u8 min_voltage_level[I915_MAX_PIPES]; struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 55252e1b26f1..ef75a913f05b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1019,6 +1019,11 @@ struct drm_i915_private { const struct intel_cdclk_vals *table; int force_min_cdclk; + + /* minimum acceptable cdclk for each pipe */ + int min_cdclk[I915_MAX_PIPES]; + /* minimum acceptable voltage level for each pipe */ + u8 min_voltage_level[I915_MAX_PIPES]; } cdclk; /** @@ -1079,10 +1084,6 @@ struct drm_i915_private { * any crtc lock is sufficient, for writing must hold all of them. */ u8 active_pipes; - /* minimum acceptable cdclk for each pipe */ - int min_cdclk[I915_MAX_PIPES]; - /* minimum acceptable voltage level for each pipe */ - u8 min_voltage_level[I915_MAX_PIPES]; int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];