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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id n17sm7297651pgg.6.2020.08.13.23.58.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:32 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 19/31][SRU][OEM-5.6] drm/i915: Add pre/post plane updates for SAGV Date: Fri, 14 Aug 2020 14:57:28 +0800 Message-Id: <20200814065740.276039-20-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.51; envelope-from=vicamo@gmail.com; helo=mail-pj1-f51.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 Lets have a unified way to handle SAGV changes, espoecially considering the upcoming Gen12 changes. Current "standard" way of doing this in commit_tail is pre/post plane updates, when everything which has to be forbidden and not supported in new config has to be restricted before update and relaxed after plane update. v2: - Removed unneeded returns(Ville) Reviewed-by: Ville Syrjälä Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200415143911.10244-5-stanislav.lisovskiy@intel.com (cherry picked from commit 680e1af713d92940e39a313a8592b13a6885a14c) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_display.c | 13 ++++--------- drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/intel_pm.h | 2 ++ 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ebafe88572ba..ab250d7ae628 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15461,12 +15461,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_set_cdclk_pre_plane_update(state); - /* - * SKL workaround: bspec recommends we disable the SAGV when we - * have more then one pipe enabled - */ - if (!intel_can_enable_sagv(state)) - intel_disable_sagv(dev_priv); + intel_sagv_pre_plane_update(state); intel_modeset_verify_disabled(dev_priv, state); } @@ -15563,11 +15558,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_check_cpu_fifo_underruns(dev_priv); intel_check_pch_fifo_underruns(dev_priv); - if (state->modeset) + if (state->modeset) { intel_verify_planes(state); - if (state->modeset && intel_can_enable_sagv(state)) - intel_enable_sagv(dev_priv); + intel_sagv_post_plane_update(state); + } drm_atomic_helper_commit_hw_done(&state->base); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9e92f8658b50..ba1e8cc785d7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3743,6 +3743,22 @@ intel_disable_sagv(struct drm_i915_private *dev_priv) return 0; } +void intel_sagv_pre_plane_update(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + + if (!intel_can_enable_sagv(state)) + intel_disable_sagv(dev_priv); +} + +void intel_sagv_post_plane_update(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + + if (intel_can_enable_sagv(state)) + intel_enable_sagv(dev_priv); +} + static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) { struct drm_device *dev = crtc_state->uapi.crtc->dev; diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index d60a85421c5a..9a6036ab0f90 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -44,6 +44,8 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv); bool intel_can_enable_sagv(struct intel_atomic_state *state); int intel_enable_sagv(struct drm_i915_private *dev_priv); int intel_disable_sagv(struct drm_i915_private *dev_priv); +void intel_sagv_pre_plane_update(struct intel_atomic_state *state); +void intel_sagv_post_plane_update(struct intel_atomic_state *state); bool skl_wm_level_equals(const struct skl_wm_level *l1, const struct skl_wm_level *l2); bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,