diff mbox series

[v2,1/1,SRU,OEM-5.6] UBUNTU: SAUCE: pci: s3 resume takes too long time, around 7s

Message ID 20200511095323.28427-2-koba.ko@canonical.com
State New
Headers show
Series UBUNTU: SAUCE: pci: Speed up the process of s3 resume | expand

Commit Message

Koba Ko May 11, 2020, 9:53 a.m. UTC 
From: Koba Ko <koba.ko@canonical.com>

From: https://lore.kernel.org/linux-pci/20200416083245.73957-1-mika.westerberg@linux.intel.com/

BugLink: https://bugs.launchpad.net/bugs/1876844

Since PCIe spec mandates that all downstream ports that support
speeds greater than 5 GT/s must support data link layer active
reporting so use that here to determine when the delay should
be issued.

Tested-by: Kai-Heng Feng <kai.heng.feng at canonical.com>
Signed-off-by: Mika Westerberg <mika.westerberg at linux.intel.com>
Signed-off-by: Koba Ko <koba.ko@canonical.com>
(cherry picked from commit d5815dd17e866ad81503057e001b72ba473573d9)
Signed-off-by: Koba Ko <koba.ko@canonical.com>
---
 drivers/pci/pci.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Comments

Koba Ko May 13, 2020, 5:44 a.m. UTC | #1 
On Mon, May 11, 2020 at 5:53 PM <koba.ko@canonical.com> wrote:

> From: Koba Ko <koba.ko@canonical.com>
>
> From:
> https://lore.kernel.org/linux-pci/20200416083245.73957-1-mika.westerberg@linux.intel.com/
>
> BugLink: https://bugs.launchpad.net/bugs/1876844
>
> Since PCIe spec mandates that all downstream ports that support
> speeds greater than 5 GT/s must support data link layer active
> reporting so use that here to determine when the delay should
> be issued.
>
> Tested-by: Kai-Heng Feng <kai.heng.feng at canonical.com>
> Signed-off-by: Mika Westerberg <mika.westerberg at linux.intel.com>
> Signed-off-by: Koba Ko <koba.ko@canonical.com>
> (cherry picked from commit d5815dd17e866ad81503057e001b72ba473573d9)
> Signed-off-by: Koba Ko <koba.ko@canonical.com>
> ---
>  drivers/pci/pci.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index d828ca835a98..aa4d4de1e2e1 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -4765,7 +4765,13 @@ void pci_bridge_wait_for_secondary_bus(struct
> pci_dev *dev)
>         if (!pcie_downstream_port(dev))
>                 return;
>
> -       if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
> +       /*
> +        * Since PCIe spec mandates that all downstream ports that
> +        * support speeds greater than 5 GT/s must support data link
> +        * layer active reporting we use that here to determine when the
> +        * delay should be issued.
> +        */
> +       if (!dev->link_active_reporting) {
>                 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
>                 msleep(delay);
>         } else {
> --
> 2.25.1
>
> Should be clarified the source of patch on line of cherry-pick.
diff mbox series

Patch

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index d828ca835a98..aa4d4de1e2e1 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4765,7 +4765,13 @@  void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
 	if (!pcie_downstream_port(dev))
 		return;
 
-	if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
+	/*
+	 * Since PCIe spec mandates that all downstream ports that
+	 * support speeds greater than 5 GT/s must support data link
+	 * layer active reporting we use that here to determine when the
+	 * delay should be issued.
+	 */
+	if (!dev->link_active_reporting) {
 		pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
 		msleep(delay);
 	} else {