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[OEM-5.6,25/37] drm/i915/tgl: Add Wa number to WaAllowPMDepthAndInvocationCountAccessFromUMD

Message ID 20200324143306.250696-26-tjaalton@ubuntu.com
State New
Headers show
Series drm/i915: Enable Tiger Lake | expand

Commit Message

Timo Aaltonen March 24, 2020, 2:32 p.m. UTC
From: José Roberto de Souza <jose.souza@intel.com>

BugLink: https://bugs.launchpad.net/bugs/1868727

Just to make easier to check that the Wa was implemetend when
comparing to the number in BSpec.

BSpec: 52890
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-10-jose.souza@intel.com
(cherry picked from drm-intel-next commit f5e5a33037a8272d545f022f4f28d20948fd4cb8)
Signed-off-by: Timo Aaltonen <timo.aaltonen@canonical.com>
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series


diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8dae65e76610..dd6eabced7d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1247,6 +1247,7 @@  static void tgl_whitelist_build(struct intel_engine_cs *engine)
 		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
+		 * Wa_1408556865:tgl
 		 * This covers 4 registers which are next to one another :