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Thu, 9 May 2019 19:23:57 +0000 Received: from BYAPR12MB2662.namprd12.prod.outlook.com ([fe80::903a:7fa4:3729:3b67]) by BYAPR12MB2662.namprd12.prod.outlook.com ([fe80::903a:7fa4:3729:3b67%3]) with mapi id 15.20.1878.019; Thu, 9 May 2019 19:23:57 +0000 From: "Naru, Kim" To: "kernel-team@lists.ubuntu.com" Subject: [Bionic][PATCH 5/5] x86/MCE/AMD: Fix the thresholding machinery initialization order Thread-Topic: [Bionic][PATCH 5/5] x86/MCE/AMD: Fix the thresholding machinery initialization order Thread-Index: AQHVBpy/ckKTjecYCkWhotSPs1GvXg== Date: Thu, 9 May 2019 19:23:56 +0000 Message-ID: <20190509192345.5321-6-kim.naru@amd.com> References: <20190509192345.5321-1-kim.naru@amd.com> In-Reply-To: <20190509192345.5321-1-kim.naru@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [165.204.53.122] x-clientproxiedby: BYAPR05CA0097.namprd05.prod.outlook.com (2603:10b6:a03:e0::38) To BYAPR12MB2662.namprd12.prod.outlook.com (2603:10b6:a03:69::23) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Kim.Naru@amd.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR12MB2695; H:BYAPR12MB2662.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: c/PsXwPVw/OEELf+LeHZgMY5MkWktVV/YQb7XAvcQa+3+ErwOcgmx+PICGBzj6PHD/IXh6IGfOUO8FzJvC5AOdaSkLxo29wGKHUG5MRmj6Z/mfufh6g4McwKa3hvWBJ4RZ/gHrJ5vDoNSvlyfV1v6+2uLaRaynkvjHLmjDzZtzvMR58HgPWYv2lIUzHSmNrxDcenWzpNsn8161vDk9bBRgv/bTlKetHdcEZEmjXFAqGCCD2pV096JlemQrSPrsDLsakbApeRgXPGFZsT+zxiEfm+M3VVUgWEIPkuD2JeuRR9xlMfnY3ws1pfjGwH20DB+KSPSHIof4ek+iXwkZ2nRWRfR4Isz1KtpYoZXZMQlB8DbdJBPSRlpdgQRaC0AzVXHPOs+6DPVqXjzl+FoaJrXRQyeZRmvkITf7BF8//NkWg= Content-ID: <136AE598BA80C4479288AADCB7FC5AAC@namprd12.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e4c86a15-a9ad-4797-86c9-08d6d4b3e175 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 May 2019 19:23:56.9212 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2695 X-Mailman-Approved-At: Wed, 15 May 2019 02:22:08 +0000 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1819485 x86/MCE/AMD: Fix the thresholding machinery initialization order Currently, the code sets up the thresholding interrupt vector and only then goes about initializing the thresholding banks. Which is wrong, because an early thresholding interrupt would cause a NULL pointer dereference when accessing those banks and prevent the machine from booting. Therefore, set the thresholding interrupt vector only *after* having initialized the banks successfully. Fixes: 18807ddb7f88 ("x86/mce/AMD: Reset Threshold Limit after logging error") Reported-by: Rafał Miłecki Reported-by: John Clemens (backported from commit 60c8144afc287ef09ce8c1230c6aa972659ba1bb) Signed-off-by: Borislav Petkov Tested-by: Rafał Miłecki Tested-by: John Clemens Cc: Aravind Gopalakrishnan Cc: linux-edac@vger.kernel.org Cc: stable@vger.kernel.org Cc: Tony Luck Cc: x86@kernel.org Cc: Yazen Ghannam Link: https://lkml.kernel.org/r/20181127101700.2964-1-zajec5@gmail.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=201291 --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 6ac306cd27fe..8f344bcbfec7 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -56,7 +56,7 @@ /* Threshold LVT offset is at MSR0xC0000410[15:12] */ #define SMCA_THR_LVT_OFF 0xF000 -static bool thresholding_en; +static bool thresholding_irq_en; static const char * const th_names[] = { "load_store", @@ -533,9 +533,8 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, set_offset: offset = setup_APIC_mce_threshold(offset, new); - - if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) - mce_threshold_vector = amd_threshold_interrupt; + if (offset == new) + thresholding_irq_en = true; done: mce_threshold_block_init(&b, offset); @@ -1345,9 +1344,6 @@ int mce_threshold_remove_device(unsigned int cpu) { unsigned int bank; - if (!thresholding_en) - return 0; - for (bank = 0; bank < mca_cfg.banks; ++bank) { if (!(per_cpu(bank_map, cpu) & (1 << bank))) continue; @@ -1365,9 +1361,6 @@ int mce_threshold_create_device(unsigned int cpu) struct threshold_bank **bp; int err = 0; - if (!thresholding_en) - return 0; - bp = per_cpu(threshold_banks, cpu); if (bp) return 0; @@ -1396,9 +1389,6 @@ static __init int threshold_init_device(void) { unsigned lcpu = 0; - if (mce_threshold_vector == amd_threshold_interrupt) - thresholding_en = true; - /* to hit CPUs online before the notifier is up */ for_each_online_cpu(lcpu) { int err = mce_threshold_create_device(lcpu); @@ -1407,6 +1397,9 @@ static __init int threshold_init_device(void) return err; } + if (thresholding_irq_en) + mce_threshold_vector = amd_threshold_interrupt; + return 0; } /*