diff mbox series

[SRU,Trusty,3/3] UBUNTU: SAUCE: x86/speculation: Move RSB_CTXSW hunk

Message ID 20181121173113.13474-4-juergh@canonical.com
State New
Headers show
Series Cleanups for CVE-2017-5715 (Spectre v2) | expand

Commit Message

Juerg Haefliger Nov. 21, 2018, 5:31 p.m. UTC 
Move the RSB_CTXSW hunk further up in spectre_v2_select_mitigation() to
match upstream. No functional changes.

CVE-2017-5715

Signed-off-by: Juerg Haefliger <juergh@canonical.com>
---
 arch/x86/kernel/cpu/bugs.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)
diff mbox series

Patch

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index c86a805557fc..4a8b8fedffe1 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -428,6 +428,17 @@  retpoline_auto:
 	spectre_v2_enabled = mode;
 	pr_info("%s\n", spectre_v2_strings[mode]);
 
+	/*
+	 * If spectre v2 protection has been enabled, unconditionally fill
+	 * RSB during a context switch; this protects against two independent
+	 * issues:
+	 *
+	 *	- RSB underflow (and switch to BTB) on Skylake+
+	 *	- SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
+	 */
+	setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
+	pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
+
 	/*
 	 * Initialize Indirect Branch Prediction Barrier if supported and not
 	 * disabled on the commandline
@@ -462,17 +473,6 @@  retpoline_auto:
 			set_ibrs_enabled(1);
 		}
 	}
-
-	/*
-	 * If spectre v2 protection has been enabled, unconditionally fill
-	 * RSB during a context switch; this protects against two independent
-	 * issues:
-	 *
-	 *	- RSB underflow (and switch to BTB) on Skylake+
-	 *	- SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
-	 */
-	setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
-	pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
 }
 
 #undef pr_fmt