| Message ID | 1613762559-30398-2-git-send-email-mahantesh@nvidia.com |
|---|---|
| State | New |
| Headers | show |
| Series | UBUNTU: SAUCE: pka: Use memory addresses defined in ACPI table | expand |
On 19.02.21 20:22, Mahantesh Salimath wrote: > Buglink: https://bugs.launchpad.net/ubuntu/+source/linux-bluefield/+bug/1916274 > > * Read platform dependant memory addresses from ACPI and > remove these memory definitions from driver code. > > * Defining platform dependant memory addresses in ACPI > removes platform dependant code from driver. > It is also a better design as it will allow to > accomodate address changes with platform. > > Signed-off-by: Mahantesh Salimath <mahantesh@nvidia.com> > Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com> > Singed-off-by: Mahantesh Salimath <mahantesh@nvidia.com> Acked-by: Stefan Bader <stefan.bader@canonical.com> > --- Formal review only (no code review). The BugLink URL should be shortened to https://bugs.launchpad.net/bugs/1916274 (this is the form that should always work, even if the source name or project might change). Also it is less to type. For future reference, we can make the change when applying for this patch. -Stefan > > diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h > index becb45e..07cbcda 100644 > --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h > +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h > @@ -66,75 +66,74 @@ > > // EIP154 CSRS: > > -#define PKA_EIP154_ADDR 0x400000 > // Global Control Space CSR addresses/offsets. These are accessed from the > // ARM as 8 byte reads/writes however only the bottom 32 bits are implemented. > -#define PKA_CLOCK_SWITCH_ADDR (0x11C68 | PKA_EIP154_ADDR) > -#define PKA_CLK_FORCE_ADDR (0x11C80 | PKA_EIP154_ADDR) > -#define MODE_SELECTION_ADDR (0x11C88 | PKA_EIP154_ADDR) > -#define PKA_PROT_STATUS_ADDR (0x11C90 | PKA_EIP154_ADDR) > -#define PKA_OPTIONS_ADDR (0x11DF0 | PKA_EIP154_ADDR) > -#define PKA_VERSION_ADDR (0x11DF8 | PKA_EIP154_ADDR) > +#define PKA_CLOCK_SWITCH_ADDR 0x11C68 > +#define PKA_CLK_FORCE_ADDR 0x11C80 > +#define MODE_SELECTION_ADDR 0x11C88 > +#define PKA_PROT_STATUS_ADDR 0x11C90 > +#define PKA_OPTIONS_ADDR 0x11DF0 > +#define PKA_VERSION_ADDR 0x11DF8 > > // Advanced Interrupt Controller CSR addresses/offsets. These are accessed > // from the ARM as 8 byte reads/writes however only the bottom 32 bits are > // implemented. > -#define AIC_POL_CTRL_ADDR (0x11E00 | PKA_EIP154_ADDR) > -#define AIC_TYPE_CTRL_ADDR (0x11E08 | PKA_EIP154_ADDR) > -#define AIC_ENABLE_CTRL_ADDR (0x11E10 | PKA_EIP154_ADDR) > -#define AIC_RAW_STAT_ADDR (0x11E18 | PKA_EIP154_ADDR) > -#define AIC_ENABLE_SET_ADDR (0x11E18 | PKA_EIP154_ADDR) > -#define AIC_ENABLED_STAT_ADDR (0x11E20 | PKA_EIP154_ADDR) > -#define AIC_ACK_ADDR (0x11E20 | PKA_EIP154_ADDR) > -#define AIC_ENABLE_CLR_ADDR (0x11E28 | PKA_EIP154_ADDR) > -#define AIC_OPTIONS_ADDR (0x11E30 | PKA_EIP154_ADDR) > -#define AIC_VERSION_ADDR (0x11E38 | PKA_EIP154_ADDR) > +#define AIC_POL_CTRL_ADDR 0x11E00 > +#define AIC_TYPE_CTRL_ADDR 0x11E08 > +#define AIC_ENABLE_CTRL_ADDR 0x11E10 > +#define AIC_RAW_STAT_ADDR 0x11E18 > +#define AIC_ENABLE_SET_ADDR 0x11E18 > +#define AIC_ENABLED_STAT_ADDR 0x11E20 > +#define AIC_ACK_ADDR 0x11E20 > +#define AIC_ENABLE_CLR_ADDR 0x11E28 > +#define AIC_OPTIONS_ADDR 0x11E30 > +#define AIC_VERSION_ADDR 0x11E38 > > // The True Random Number Generator CSR addresses/offsets. These are accessed > // from the ARM as 8 byte reads/writes however only the bottom 32 bits are > // implemented. > -#define TRNG_OUTPUT_0_ADDR (0x12000 | PKA_EIP154_ADDR) > -#define TRNG_OUTPUT_1_ADDR (0x12008 | PKA_EIP154_ADDR) > -#define TRNG_OUTPUT_2_ADDR (0x12010 | PKA_EIP154_ADDR) > -#define TRNG_OUTPUT_3_ADDR (0x12018 | PKA_EIP154_ADDR) > -#define TRNG_STATUS_ADDR (0x12020 | PKA_EIP154_ADDR) > -#define TRNG_INTACK_ADDR (0x12020 | PKA_EIP154_ADDR) > -#define TRNG_CONTROL_ADDR (0x12028 | PKA_EIP154_ADDR) > -#define TRNG_CONFIG_ADDR (0x12030 | PKA_EIP154_ADDR) > -#define TRNG_ALARMCNT_ADDR (0x12038 | PKA_EIP154_ADDR) > -#define TRNG_FROENABLE_ADDR (0x12040 | PKA_EIP154_ADDR) > -#define TRNG_FRODETUNE_ADDR (0x12048 | PKA_EIP154_ADDR) > -#define TRNG_ALARMMASK_ADDR (0x12050 | PKA_EIP154_ADDR) > -#define TRNG_ALARMSTOP_ADDR (0x12058 | PKA_EIP154_ADDR) > -#define TRNG_BLOCKCNT_ADDR (0x120E8 | PKA_EIP154_ADDR) > -#define TRNG_OPTIONS_ADDR (0x120F0 | PKA_EIP154_ADDR) > +#define TRNG_OUTPUT_0_ADDR 0x12000 > +#define TRNG_OUTPUT_1_ADDR 0x12008 > +#define TRNG_OUTPUT_2_ADDR 0x12010 > +#define TRNG_OUTPUT_3_ADDR 0x12018 > +#define TRNG_STATUS_ADDR 0x12020 > +#define TRNG_INTACK_ADDR 0x12020 > +#define TRNG_CONTROL_ADDR 0x12028 > +#define TRNG_CONFIG_ADDR 0x12030 > +#define TRNG_ALARMCNT_ADDR 0x12038 > +#define TRNG_FROENABLE_ADDR 0x12040 > +#define TRNG_FRODETUNE_ADDR 0x12048 > +#define TRNG_ALARMMASK_ADDR 0x12050 > +#define TRNG_ALARMSTOP_ADDR 0x12058 > +#define TRNG_BLOCKCNT_ADDR 0x120E8 > +#define TRNG_OPTIONS_ADDR 0x120F0 > > // Control register address/offset. This is accessed from the ARM using 8 > // byte reads/writes however only the bottom 32 bits are implemented. > -#define PKA_MASTER_SEQ_CTRL_ADDR (0x27F90 | PKA_EIP154_ADDR) > +#define PKA_MASTER_SEQ_CTRL_ADDR 0x27F90 > > // Ring CSRs: These are all accessed from the ARM using 8 byte reads/writes > // however only the bottom 32 bits are implemented. > > // Ring 0 CSRS > -#define COMMAND_COUNT_0_ADDR (0x80080 | PKA_EIP154_ADDR) > -#define RESULT_COUNT_0_ADDR (0x80088 | PKA_EIP154_ADDR) > -#define IRQ_THRESH_0_ADDR (0x80090 | PKA_EIP154_ADDR) > +#define COMMAND_COUNT_0_ADDR 0x80080 > +#define RESULT_COUNT_0_ADDR 0x80088 > +#define IRQ_THRESH_0_ADDR 0x80090 > > // Ring 1 CSRS: > -#define COMMAND_COUNT_1_ADDR (0x90080 | PKA_EIP154_ADDR) > -#define RESULT_COUNT_1_ADDR (0x90088 | PKA_EIP154_ADDR) > -#define IRQ_THRESH_1_ADDR (0x90090 | PKA_EIP154_ADDR) > +#define COMMAND_COUNT_1_ADDR 0x90080 > +#define RESULT_COUNT_1_ADDR 0x90088 > +#define IRQ_THRESH_1_ADDR 0x90090 > > // Ring 2 CSRS: > -#define COMMAND_COUNT_2_ADDR (0xA0080 | PKA_EIP154_ADDR) > -#define RESULT_COUNT_2_ADDR (0xA0088 | PKA_EIP154_ADDR) > -#define IRQ_THRESH_2_ADDR (0xA0090 | PKA_EIP154_ADDR) > +#define COMMAND_COUNT_2_ADDR 0xA0080 > +#define RESULT_COUNT_2_ADDR 0xA0088 > +#define IRQ_THRESH_2_ADDR 0xA0090 > > // Ring 3 CSRS: > -#define COMMAND_COUNT_3_ADDR (0xB0080 | PKA_EIP154_ADDR) > -#define RESULT_COUNT_3_ADDR (0xB0088 | PKA_EIP154_ADDR) > -#define IRQ_THRESH_3_ADDR (0xB0090 | PKA_EIP154_ADDR) > +#define COMMAND_COUNT_3_ADDR 0xB0080 > +#define RESULT_COUNT_3_ADDR 0xB0088 > +#define IRQ_THRESH_3_ADDR 0xB0090 > > // EIP154 RAM regions: Note that the FARM_PROG_RAM_X address range overlaps > // with the FARM_DATA_RAM_X and FARM_DATA_RAM_X_EXT address ranges. This > @@ -164,115 +163,100 @@ > // PKA Farm Data RAM extension size : 4KB --> 8KB > // PKA Farm Program RAM size : 8KB --> 16KB > // > -#define PKA_BUFFER_RAM_BASE (0x00000 | PKA_EIP154_ADDR) > +#define PKA_BUFFER_RAM_BASE 0x00000 > #define PKA_BUFFER_RAM_SIZE MEM_SIZE_16KB // 0x00000...0x03FFF > > -#define PKA_SECURE_RAM_BASE (0x20000 | PKA_EIP154_ADDR) > +#define PKA_SECURE_RAM_BASE 0x20000 > #define PKA_SECURE_RAM_SIZE MEM_SIZE_16KB // 0x20000...0x23FFF > > -#define PKA_MASTER_PROG_RAM_BASE (0x30000 | PKA_EIP154_ADDR) > +#define PKA_MASTER_PROG_RAM_BASE 0x30000 > #define PKA_MASTER_PROG_RAM_SIZE MEM_SIZE_64KB // 0x30000...0x3FFFF > > -#define FARM_DATA_RAM_0_BASE (0x40000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_0_BASE 0x40000 > #define FARM_DATA_RAM_0_SIZE MEM_SIZE_8KB // 0x40000...0x41FFF > -#define FARM_DATA_RAM_0_EXT_BASE (0x42000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_0_EXT_BASE 0x42000 > #define FARM_DATA_RAM_0_EXT_SIZE MEM_SIZE_8KB // 0x42000...0x43FFF > -#define FARM_PROG_RAM_0_BASE (0x40000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_0_BASE 0x40000 > #define FARM_PROG_RAM_0_SIZE MEM_SIZE_16KB // 0x40000...0x43FFF > -#define FARM_DATA_RAM_1_BASE (0x44000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_1_BASE 0x44000 > #define FARM_DATA_RAM_1_SIZE MEM_SIZE_8KB // 0x44000...0x45FFF > -#define FARM_DATA_RAM_1_EXT_BASE (0x46000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_1_EXT_BASE 0x46000 > #define FARM_DATA_RAM_1_EXT_SIZE MEM_SIZE_8KB // 0x46000...0x47FFF > -#define FARM_PROG_RAM_1_BASE (0x44000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_1_BASE 0x44000 > #define FARM_PROG_RAM_1_SIZE MEM_SIZE_16KB // 0x44000...0x47FFF > -#define FARM_DATA_RAM_2_BASE (0x48000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_2_BASE 0x48000 > #define FARM_DATA_RAM_2_SIZE MEM_SIZE_8KB // 0x48000...0x49FFF > -#define FARM_DATA_RAM_2_EXT_BASE (0x4A000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_2_EXT_BASE 0x4A000 > #define FARM_DATA_RAM_2_EXT_SIZE MEM_SIZE_8KB // 0x4A000...0x4BFFF > -#define FARM_PROG_RAM_2_BASE (0x48000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_2_BASE 0x48000 > #define FARM_PROG_RAM_2_SIZE MEM_SIZE_16KB // 0x48000...0x4BFFF > -#define FARM_DATA_RAM_3_BASE (0x4C000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_3_BASE 0x4C000 > #define FARM_DATA_RAM_3_SIZE MEM_SIZE_8KB // 0x4C000...0x4DFFF > -#define FARM_DATA_RAM_3_EXT_BASE (0x4E000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_3_EXT_BASE 0x4E000 > #define FARM_DATA_RAM_3_EXT_SIZE MEM_SIZE_8KB // 0x4E000...0x4FFFF > -#define FARM_PROG_RAM_3_BASE (0x4C000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_3_BASE 0x4C000 > #define FARM_PROG_RAM_3_SIZE MEM_SIZE_16KB // 0x4C000...0x4FFFF > -#define FARM_DATA_RAM_4_BASE (0x50000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_4_BASE 0x50000 > #define FARM_DATA_RAM_4_SIZE MEM_SIZE_8KB // 0x50000...0x51FFF > -#define FARM_DATA_RAM_4_EXT_BASE (0x52000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_4_EXT_BASE 0x52000 > #define FARM_DATA_RAM_4_EXT_SIZE MEM_SIZE_8KB // 0x52000...0x53FFF > -#define FARM_PROG_RAM_4_BASE (0x50000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_4_BASE 0x50000 > #define FARM_PROG_RAM_4_SIZE MEM_SIZE_16KB // 0x50000...0x53FFF > -#define FARM_DATA_RAM_5_BASE (0x54000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_5_BASE 0x54000 > #define FARM_DATA_RAM_5_SIZE MEM_SIZE_8KB // 0x54000...0x55FFF > -#define FARM_DATA_RAM_5_EXT_BASE (0x56000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_5_EXT_BASE 0x56000 > #define FARM_DATA_RAM_5_EXT_SIZE MEM_SIZE_8KB // 0x56000...0x57FFF > -#define FARM_PROG_RAM_5_BASE (0x54000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_5_BASE 0x54000 > #define FARM_PROG_RAM_5_SIZE MEM_SIZE_16KB // 0x54000...0x57FFF > > // PKA Buffer RAM offsets. These are NOT real CSR's but instead are > // specific offset/addresses within the EIP154 PKA_BUFFER_RAM. > > // Ring 0: > -#define RING_CMMD_BASE_0_ADDR (0x00000 | PKA_EIP154_ADDR) > -#define RING_RSLT_BASE_0_ADDR (0x00010 | PKA_EIP154_ADDR) > -#define RING_SIZE_TYPE_0_ADDR (0x00020 | PKA_EIP154_ADDR) > -#define RING_RW_PTRS_0_ADDR (0x00028 | PKA_EIP154_ADDR) > -#define RING_RW_STAT_0_ADDR (0x00030 | PKA_EIP154_ADDR) > +#define RING_CMMD_BASE_0_ADDR 0x00000 > +#define RING_RSLT_BASE_0_ADDR 0x00010 > +#define RING_SIZE_TYPE_0_ADDR 0x00020 > +#define RING_RW_PTRS_0_ADDR 0x00028 > +#define RING_RW_STAT_0_ADDR 0x00030 > > // Ring 1 > -#define RING_CMMD_BASE_1_ADDR (0x00040 | PKA_EIP154_ADDR) > -#define RING_RSLT_BASE_1_ADDR (0x00050 | PKA_EIP154_ADDR) > -#define RING_SIZE_TYPE_1_ADDR (0x00060 | PKA_EIP154_ADDR) > -#define RING_RW_PTRS_1_ADDR (0x00068 | PKA_EIP154_ADDR) > -#define RING_RW_STAT_1_ADDR (0x00070 | PKA_EIP154_ADDR) > +#define RING_CMMD_BASE_1_ADDR 0x00040 > +#define RING_RSLT_BASE_1_ADDR 0x00050 > +#define RING_SIZE_TYPE_1_ADDR 0x00060 > +#define RING_RW_PTRS_1_ADDR 0x00068 > +#define RING_RW_STAT_1_ADDR 0x00070 > > // Ring 2 > -#define RING_CMMD_BASE_2_ADDR (0x00080 | PKA_EIP154_ADDR) > -#define RING_RSLT_BASE_2_ADDR (0x00090 | PKA_EIP154_ADDR) > -#define RING_SIZE_TYPE_2_ADDR (0x000A0 | PKA_EIP154_ADDR) > -#define RING_RW_PTRS_2_ADDR (0x000A8 | PKA_EIP154_ADDR) > -#define RING_RW_STAT_2_ADDR (0x000B0 | PKA_EIP154_ADDR) > +#define RING_CMMD_BASE_2_ADDR 0x00080 > +#define RING_RSLT_BASE_2_ADDR 0x00090 > +#define RING_SIZE_TYPE_2_ADDR 0x000A0 > +#define RING_RW_PTRS_2_ADDR 0x000A8 > +#define RING_RW_STAT_2_ADDR 0x000B0 > > // Ring 3 > -#define RING_CMMD_BASE_3_ADDR (0x000C0 | PKA_EIP154_ADDR) > -#define RING_RSLT_BASE_3_ADDR (0x000D0 | PKA_EIP154_ADDR) > -#define RING_SIZE_TYPE_3_ADDR (0x000E0 | PKA_EIP154_ADDR) > -#define RING_RW_PTRS_3_ADDR (0x000E8 | PKA_EIP154_ADDR) > -#define RING_RW_STAT_3_ADDR (0x000F0 | PKA_EIP154_ADDR) > +#define RING_CMMD_BASE_3_ADDR 0x000C0 > +#define RING_RSLT_BASE_3_ADDR 0x000D0 > +#define RING_SIZE_TYPE_3_ADDR 0x000E0 > +#define RING_RW_PTRS_3_ADDR 0x000E8 > +#define RING_RW_STAT_3_ADDR 0x000F0 > > // Ring Options > -#define PKA_RING_OPTIONS_ADDR (0x07FF8 | PKA_EIP154_ADDR) > +#define PKA_RING_OPTIONS_ADDR 0x07FF8 > > -// Note the registers/memory below include MiCA specific PKA Control/Status > -// registers and the 64K RAM's that the EIP-154 calls Host Memory. > - > -// Note that Window RAM size is 64K however only the low 16K can be accessed. > -#define PKA_WINDOW_RAM_BASE 0x500000 > -#define PKA_WINDOW_RAM_SIZE MEM_SIZE_64KB > +// Alternate Window RAM size > #define PKA_WINDOW_RAM_REGION_SIZE MEM_SIZE_16KB > > -#define PKA_WINDOW_RAM_REGION_0_BASE 0x600000 > -#define PKA_WINDOW_RAM_REGION_0_SIZE PKA_WINDOW_RAM_REGION_SIZE > -#define PKA_WINDOW_RAM_REGION_1_BASE 0x610000 > -#define PKA_WINDOW_RAM_REGION_1_SIZE PKA_WINDOW_RAM_REGION_SIZE > -#define PKA_WINDOW_RAM_REGION_2_BASE 0x620000 > -#define PKA_WINDOW_RAM_REGION_2_SIZE PKA_WINDOW_RAM_REGION_SIZE > -#define PKA_WINDOW_RAM_REGION_3_BASE 0x630000 > -#define PKA_WINDOW_RAM_REGION_3_SIZE PKA_WINDOW_RAM_REGION_SIZE > - > // Currently, we do not use these MiCA specific CSRs. > -#define PKI_EXT_CSR_START_ADDR 0x510000 > > // The PKI (not EIP154) CSR address/offsets: These are all addressed as > // 8-byte registers. > -#define PKA_INT_MASK_ADDR (0x00 | PKI_EXT_CSR_START_ADDR) > -#define PKA_INT_MASK_SET_ADDR (0x08 | PKI_EXT_CSR_START_ADDR) > -#define PKA_INT_MASK_RESET_ADDR (0x10 | PKI_EXT_CSR_START_ADDR) > -#define PKA_ZEROIZE_ADDR (0x40 | PKI_EXT_CSR_START_ADDR) > -#define TST_FRO_ADDR (0x50 | PKI_EXT_CSR_START_ADDR) > -#define FRO_COUNT_ADDR (0x58 | PKI_EXT_CSR_START_ADDR) > -#define PKA_PARITY_CTL_ADDR (0x60 | PKI_EXT_CSR_START_ADDR) > -#define PKA_PARITY_STAT_ADDR (0x68 | PKI_EXT_CSR_START_ADDR) > +#define PKA_INT_MASK_ADDR 0x00 > +#define PKA_INT_MASK_SET_ADDR 0x08 > +#define PKA_INT_MASK_RESET_ADDR 0x10 > +#define PKA_ZEROIZE_ADDR 0x40 > +#define TST_FRO_ADDR 0x50 > +#define FRO_COUNT_ADDR 0x58 > +#define PKA_PARITY_CTL_ADDR 0x60 > +#define PKA_PARITY_STAT_ADDR 0x68 > > #endif // __PKA_ADDRS_H__ > diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h > index 4cda85d..b590477 100644 > --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h > +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h > @@ -53,13 +53,10 @@ > // and ring spacing. > #define PKA_RING_WORDS_ADDR PKA_BUFFER_RAM_BASE > #define PKA_RING_CNTRS_ADDR COMMAND_COUNT_0_ADDR > -#define PKA_RING_MEM_0_BASE PKA_WINDOW_RAM_BASE > -#define PKA_RING_MEM_1_BASE PKA_WINDOW_RAM_REGION_0_BASE > > #define PKA_RING_WORDS_SIZE 0x40 // 64 bytes > #define PKA_RING_CNTRS_SIZE 0x20 // 32 bytes (3 count registers) > -#define PKA_RING_MEM_0_SIZE PKA_WINDOW_RAM_REGION_SIZE > -#define PKA_RING_MEM_1_SIZE PKA_WINDOW_RAM_REGION_SIZE > +#define PKA_RING_MEM_SIZE 0x4000 // 16K bytes > > #define PKA_RING_WORDS_SPACING 0x40 // 64 bytes > #define PKA_RING_CNTRS_SPACING 0x10000 // 64K bytes > @@ -75,11 +72,18 @@ > #define PKA_WINDOW_RAM_RING_MEM_SIZE 0x0800 // 2KB > #define PKA_WINDOW_RAM_DATA_MEM_SIZE 0x3800 // 14KB > > +// Offset mask, common to both Window and Alternate Window RAM. > +#define PKA_WINDOW_RAM_OFFSET_MASK1 0x730000 > + > // Macro for mapping PKA Ring address into Window RAM address. It converts the > // ring address, either physical address or virtual address, to valid address > -// into the Window RAM. This is done assuming the Window RAM base and size. > -#define PKA_RING_MEM_ADDR(addr, size) \ > - (PKA_WINDOW_RAM_BASE | (((addr) & 0xffff) | \ > +// into the Window RAM. This is done assuming the Window RAM base, size and > +// mask. Here, base is the actual physical address of the Window RAM, with the > +// help of mask it is reduced to Window RAM offset within that PKA block. > +// Further, with the help of addr and size, we arrive at the Window RAM > +// offset address for a PKA Ring within the given Window RAM. > +#define PKA_RING_MEM_ADDR(base, mask, addr, size) \ > + ((base & mask) | (((addr) & 0xffff) | \ > ((((addr) & ~((size) - 1)) & 0xf0000) >> 2))) > > // PKA Master Sequencer Control/Status Register > diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c > index 4539bae..8e4141b 100644 > --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c > +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c > @@ -175,7 +175,7 @@ static int pka_dev_set_resource_config(pka_dev_shim_t *shim, > res_ptr->base = res_base; > > if (res_type == PKA_DEV_RES_TYPE_MEM) > - res_ptr->base = shim->base + res_base; > + res_ptr->base = shim->mem_res.eip154_base + res_base; > > res_ptr->size = res_size; > res_ptr->type = res_type; > @@ -267,7 +267,6 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, > uint32_t ring_cntrs_off; > uint32_t ring_mem_off; > uint32_t ring_mem_base; > - uint32_t ring_mem_size; > > uint32_t shim_ring_id; > uint8_t window_ram_split; > @@ -294,7 +293,8 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, > // Configure ring information control/status words resource > ring_info_words_ptr = &ring->resources.info_words; > ring_words_off = shim_ring_id * PKA_RING_WORDS_SPACING; > - ring_info_words_ptr->base = ring_words_off + PKA_RING_WORDS_ADDR; > + ring_info_words_ptr->base = ring_words_off + shim->mem_res.eip154_base + > + PKA_RING_WORDS_ADDR; > ring_info_words_ptr->size = PKA_RING_WORDS_SIZE; > ring_info_words_ptr->type = PKA_DEV_RES_TYPE_MEM; > ring_info_words_ptr->status = PKA_DEV_RES_STATUS_UNMAPPED; > @@ -303,7 +303,8 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, > // Configure ring counters registers resource > ring_counters_ptr = &ring->resources.counters; > ring_cntrs_off = shim_ring_id * PKA_RING_CNTRS_SPACING; > - ring_counters_ptr->base = ring_cntrs_off + PKA_RING_CNTRS_ADDR; > + ring_counters_ptr->base = ring_cntrs_off + shim->mem_res.eip154_base + > + PKA_RING_CNTRS_ADDR; > ring_counters_ptr->size = PKA_RING_CNTRS_SIZE; > ring_counters_ptr->type = PKA_DEV_RES_TYPE_REG; > ring_counters_ptr->status = PKA_DEV_RES_STATUS_UNMAPPED; > @@ -314,19 +315,17 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, > if (window_ram_split == PKA_SHIM_WINDOW_RAM_SPLIT_ENABLED) > { > ring_mem_off = shim_ring_id * PKA_RING_MEM_1_SPACING; > - ring_mem_base = ring_mem_off + PKA_RING_MEM_1_BASE; > - ring_mem_size = PKA_RING_MEM_1_SIZE; > + ring_mem_base = ring_mem_off + shim->mem_res.alt_wndw_ram_0_base; > } > else > { > ring_mem_off = shim_ring_id * PKA_RING_MEM_0_SPACING; > - ring_mem_base = ring_mem_off + PKA_RING_MEM_0_BASE; > - ring_mem_size = PKA_RING_MEM_0_SIZE; > + ring_mem_base = ring_mem_off + shim->mem_res.wndw_ram_base; > } > > ring_window_ram_ptr = &ring->resources.window_ram; > ring_window_ram_ptr->base = ring_mem_base; > - ring_window_ram_ptr->size = ring_mem_size; > + ring_window_ram_ptr->size = PKA_RING_MEM_SIZE; > ring_window_ram_ptr->type = PKA_DEV_RES_TYPE_MEM; > ring_window_ram_ptr->status = PKA_DEV_RES_STATUS_UNMAPPED; > ring_window_ram_ptr->name = "PKA_RING_WINDOW"; > @@ -474,9 +473,11 @@ static int pka_dev_partition_mem(pka_dev_ring_t *ring) > rslt_desc_ring_base = ring_mem_base + cmd_desc_ring_size; > > cmd_desc_ring_base = > - PKA_RING_MEM_ADDR(cmd_desc_ring_base, window_ram_size); > + PKA_RING_MEM_ADDR(window_ram_base, shim->mem_res.wndw_ram_off_mask, > + cmd_desc_ring_base, window_ram_size); > rslt_desc_ring_base = > - PKA_RING_MEM_ADDR(rslt_desc_ring_base, window_ram_size); > + PKA_RING_MEM_ADDR(window_ram_base, shim->mem_res.wndw_ram_off_mask, > + rslt_desc_ring_base, window_ram_size); > > ring_info = ring->ring_info; > // Fill ring information. > @@ -629,7 +630,7 @@ static int pka_dev_set_ring_info(pka_dev_ring_t *ring) > // Create shim. Set shim parameters and configure shim resources. > // It returns 0 on success, a negative error code on failure. > static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > - uint64_t shim_base, uint64_t shim_size, uint8_t split) > + uint8_t split, struct pka_dev_mem_res *mem_res) > { > int ret = 0; > > @@ -652,8 +653,7 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > } > > shim->shim_id = shim_id; > - shim->base = shim_base; > - shim->size = shim_size; > + shim->mem_res = *mem_res; > > if (split) > shim->window_ram_split = PKA_SHIM_WINDOW_RAM_SPLIT_ENABLED; > @@ -674,10 +674,10 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device Buffer RAM config > ret = pka_dev_set_resource_config(shim, &shim->resources.buffer_ram, > - PKA_BUFFER_RAM_BASE, > - PKA_BUFFER_RAM_SIZE, > - PKA_DEV_RES_TYPE_MEM, > - "PKA_BUFFER_RAM"); > + PKA_BUFFER_RAM_BASE, > + PKA_BUFFER_RAM_SIZE, > + PKA_DEV_RES_TYPE_MEM, > + "PKA_BUFFER_RAM"); > if (ret) > { > PKA_ERROR(PKA_DEV, "unable to set Buffer RAM config\n"); > @@ -686,10 +686,10 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device Master Program RAM config > ret = pka_dev_set_resource_config(shim, &shim->resources.master_prog_ram, > - PKA_MASTER_PROG_RAM_BASE, > - PKA_MASTER_PROG_RAM_SIZE, > - PKA_DEV_RES_TYPE_MEM, > - "PKA_MASTER_PROG_RAM"); > + PKA_MASTER_PROG_RAM_BASE, > + PKA_MASTER_PROG_RAM_SIZE, > + PKA_DEV_RES_TYPE_MEM, > + "PKA_MASTER_PROG_RAM"); > if (ret) > { > PKA_ERROR(PKA_DEV, "unable to set Master Program RAM config\n"); > @@ -698,12 +698,12 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device Master Controller register > reg_size = PAGE_SIZE; > - reg_base = pka_dev_get_register_base(shim->base, > - PKA_MASTER_SEQ_CTRL_ADDR); > + reg_base = pka_dev_get_register_base(shim->mem_res.eip154_base, > + PKA_MASTER_SEQ_CTRL_ADDR); > ret = pka_dev_set_resource_config(shim, &shim->resources.master_seq_ctrl, > - reg_base, reg_size, > - PKA_DEV_RES_TYPE_REG, > - "PKA_MASTER_SEQ_CTRL"); > + reg_base, reg_size, > + PKA_DEV_RES_TYPE_REG, > + "PKA_MASTER_SEQ_CTRL"); > if (ret) > { > PKA_ERROR(PKA_DEV, "unable to set Master Controller register " > @@ -713,8 +713,8 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device AIC registers > reg_size = PAGE_SIZE; > - reg_base = pka_dev_get_register_base(shim->base, > - AIC_POL_CTRL_ADDR); > + reg_base = pka_dev_get_register_base(shim->mem_res.eip154_base, > + AIC_POL_CTRL_ADDR); > ret = pka_dev_set_resource_config(shim, &shim->resources.aic_csr, > reg_base, reg_size, > PKA_DEV_RES_TYPE_REG, > @@ -727,8 +727,8 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device TRNG registers > reg_size = PAGE_SIZE; > - reg_base = pka_dev_get_register_base(shim->base, > - TRNG_OUTPUT_0_ADDR); > + reg_base = pka_dev_get_register_base(shim->mem_res.eip154_base, > + TRNG_OUTPUT_0_ADDR); > ret = pka_dev_set_resource_config(shim, &shim->resources.trng_csr, > reg_base, reg_size, > PKA_DEV_RES_TYPE_REG, > @@ -741,8 +741,8 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device 'glue' logic registers > reg_size = PAGE_SIZE; > - reg_base = pka_dev_get_register_base(shim->base, > - PKA_INT_MASK_ADDR); > + reg_base = pka_dev_get_register_base(shim->mem_res.csr_base, > + PKA_INT_MASK_ADDR); > ret = pka_dev_set_resource_config(shim, &shim->resources.ext_csr, > reg_base, reg_size, > PKA_DEV_RES_TYPE_REG, > @@ -1433,16 +1433,14 @@ int pka_dev_unregister_ring(pka_dev_ring_t *ring) > } > > static pka_dev_shim_t *__pka_dev_register_shim(uint32_t shim_id, > - uint64_t shim_base, > - uint64_t shim_size) > + struct pka_dev_mem_res *mem_res) > { > pka_dev_shim_t *shim; > > uint8_t split; > int ret = 0; > > - PKA_DEBUG(PKA_DEV, "register shim id=%u, start=0x%llx end=0x%llx\n", > - shim_id, shim_base, shim_base + shim_size); > + PKA_DEBUG(PKA_DEV, "register shim id=%u\n", shim_id); > > shim = kzalloc(sizeof(pka_dev_shim_t), GFP_KERNEL); > if (!shim) > @@ -1456,7 +1454,7 @@ static pka_dev_shim_t *__pka_dev_register_shim(uint32_t shim_id, > split = PKA_SPLIT_WINDOW_RAM_MODE; > > // Create PKA shim > - ret = pka_dev_create_shim(shim, shim_id, shim_base, shim_size, split); > + ret = pka_dev_create_shim(shim, shim_id, split, mem_res); > if (ret) > { > PKA_ERROR(PKA_DEV, "failed to create shim %u\n", shim_id); > @@ -1479,14 +1477,14 @@ static pka_dev_shim_t *__pka_dev_register_shim(uint32_t shim_id, > return shim; > } > > -pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint64_t shim_base, > - uint64_t shim_size, uint8_t shim_fw_id) > +pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint8_t shim_fw_id, > + struct pka_dev_mem_res *mem_res) > { > pka_dev_shim_t *shim; > > pka_firmware_set_id(shim_fw_id); > > - shim = __pka_dev_register_shim(shim_id, shim_base, shim_size); > + shim = __pka_dev_register_shim(shim_id, mem_res); > if (shim) > { > pka_gbl_config.dev_shims[shim->shim_id] = shim; > diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h > index 5a6cc8fd..b42ab5d 100644 > --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h > +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h > @@ -159,11 +159,30 @@ typedef struct > uint8_t res_cnt; > } pka_dev_gbl_shim_res_info_t; > > +struct pka_dev_mem_res > +{ > + uint64_t eip154_base; ///< base address for eip154 mmio registers > + uint64_t eip154_size; ///< eip154 mmio register region size > + > + uint64_t wndw_ram_off_mask; ///< common offset mask for alt window ram and window ram > + uint64_t wndw_ram_base; ///< base address for window ram > + uint64_t wndw_ram_size; ///< window ram region size > + > + uint64_t alt_wndw_ram_0_base; ///< base address for alternate window ram 0 > + uint64_t alt_wndw_ram_1_base; ///< base address for alternate window ram 1 > + uint64_t alt_wndw_ram_2_base; ///< base address for alternate window ram 2 > + uint64_t alt_wndw_ram_3_base; ///< base address for alternate window ram 3 > + uint64_t alt_wndw_ram_size; ///< alternate window ram regions size > + > + uint64_t csr_base; ///< base address for csr registers > + uint64_t csr_size; ///< csr area size > +}; > + > + > /// PKA Shim structure > struct pka_dev_shim_s > { > - uint64_t base; ///< shim base address > - uint64_t size; ///< shim io memory size > + struct pka_dev_mem_res mem_res; > > uint64_t trng_err_cycle; ///< TRNG error cycle > > @@ -252,8 +271,8 @@ int pka_dev_unregister_ring(pka_dev_ring_t *ring); > > /// Register PKA IO block. This function initializes a shim and configures its > /// related resources, and returns a pointer to that ring. > -pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint64_t shim_base, > - uint64_t shim_size, uint8_t shim_fw_id); > +pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint8_t shim_fw_id, > + struct pka_dev_mem_res *mem_res); > > /// Unregister PKA IO block > int pka_dev_unregister_shim(pka_dev_shim_t *shim); > diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c > index f93efb66..2290e72 100644 > --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c > +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c > @@ -28,11 +28,30 @@ > #define PKA_DEVICE_COMPAT "mlx,mlxbf-pka" > #define PKA_RING_DEVICE_COMPAT "mlx,mlxbf-pka-ring" > > -#define PKA_DEVICE_ACPIHID "MLNXBF10" > -#define PKA_RING_DEVICE_ACPIHID "MLNXBF11" > +#define PKA_DEVICE_ACPIHID_BF1 "MLNXBF10" > +#define PKA_RING_DEVICE_ACPIHID_BF1 "MLNXBF11" > + > +#define PKA_DEVICE_ACPIHID_BF2 "MLNXBF20" > +#define PKA_RING_DEVICE_ACPIHID_BF2 "MLNXBF21" > > #define PKA_DEVICE_ACCESS_MODE 0666 > > +#define PKA_DEVICE_RES_CNT 7 > +enum pka_mem_res_idx { > + PKA_ACPI_EIP154_IDX = 0, > + PKA_ACPI_WNDW_RAM_IDX, > + PKA_ACPI_ALT_WNDW_RAM_0_IDX, > + PKA_ACPI_ALT_WNDW_RAM_1_IDX, > + PKA_ACPI_ALT_WNDW_RAM_2_IDX, > + PKA_ACPI_ALT_WNDW_RAM_3_IDX, > + PKA_ACPI_CSR_IDX > +}; > + > +enum pka_plat_type { > + PKA_PLAT_TYPE_BF1 = 0, /* Platform type Bluefield-1 */ > + PKA_PLAT_TYPE_BF2 /* Platform type Bluefield-2 */ > +}; > + > static DEFINE_MUTEX(pka_drv_lock); > > static uint32_t pka_device_cnt; > @@ -41,8 +60,35 @@ static uint32_t pka_ring_device_cnt; > const char pka_compat[] = PKA_DEVICE_COMPAT; > const char pka_ring_compat[] = PKA_RING_DEVICE_COMPAT; > > -const char pka_acpihid[] = PKA_DEVICE_ACPIHID; > -const char pka_ring_acpihid[] = PKA_RING_DEVICE_ACPIHID; > +const char pka_acpihid_bf1[] = PKA_DEVICE_ACPIHID_BF1; > +const char pka_ring_acpihid_bf1[] = PKA_RING_DEVICE_ACPIHID_BF1; > + > +const char pka_acpihid_bf2[] = PKA_DEVICE_ACPIHID_BF2; > +const char pka_ring_acpihid_bf2[] = PKA_RING_DEVICE_ACPIHID_BF2; > + > +struct pka_drv_plat_info { > + enum pka_plat_type type; > + uint8_t fw_id; > +}; > + > +static struct pka_drv_plat_info pka_drv_plat[] = { > + [PKA_PLAT_TYPE_BF1] = { > + .type = PKA_PLAT_TYPE_BF1, > + .fw_id = PKA_FIRMWARE_IMAGE_0_ID > + }, > + [PKA_PLAT_TYPE_BF2] = { > + .type = PKA_PLAT_TYPE_BF2, > + .fw_id = PKA_FIRMWARE_IMAGE_1_ID > + } > +}; > + > +static const struct acpi_device_id pka_drv_acpi_ids[] = { > + { PKA_DEVICE_ACPIHID_BF1, (kernel_ulong_t)&pka_drv_plat[PKA_PLAT_TYPE_BF1] }, > + { PKA_RING_DEVICE_ACPIHID_BF1, 0 }, > + { PKA_DEVICE_ACPIHID_BF2, (kernel_ulong_t)&pka_drv_plat[PKA_PLAT_TYPE_BF2] }, > + { PKA_RING_DEVICE_ACPIHID_BF2, 0 }, > + {}, > +}; > > struct pka_info { > struct device *dev; /* the device this info belongs to */ > @@ -59,11 +105,6 @@ struct pka_info { > #define PKA_DRIVER_FLAG_RING_DEVICE 1 > #define PKA_DRIVER_FLAG_DEVICE 2 > > -enum { > - PKA_REVISION_1 = 1, > - PKA_REVISION_2, > -}; > - > struct pka_platdata { > struct platform_device *pdev; > struct pka_info *info; > @@ -138,7 +179,7 @@ struct pka_device { > uint32_t device_id; > uint8_t fw_id; /* firmware identifier */ > struct mutex mutex; > - struct resource *resource; > + struct resource *resource[PKA_DEVICE_RES_CNT]; > pka_dev_shim_t *shim; > long irq; /* interrupt number */ > struct hwrng rng; > @@ -189,7 +230,6 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) > struct pka_ring_region *region; > pka_dev_ring_t *ring; > pka_dev_res_t *res; > - uint64_t shim_base; > uint32_t num_regions; > > ring = ring_dev->ring; > @@ -204,15 +244,13 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) > if (!ring_dev->regions) > return -ENOMEM; > > - shim_base = ring->shim->base; > - > /* Information words region */ > res = &ring->resources.info_words; > region = &ring_dev->regions[PKA_RING_REGION_WORDS_IDX]; > /* map offset to the physical address */ > region->off = > PKA_RING_REGION_INDEX_TO_OFFSET(PKA_RING_REGION_WORDS_IDX); > - region->addr = res->base + shim_base; > + region->addr = res->base; > region->size = res->size; > region->type = PKA_RING_RES_TYPE_WORDS; > region->flags |= (PKA_RING_REGION_FLAG_MMAP | > @@ -225,7 +263,7 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) > /* map offset to the physical address */ > region->off = > PKA_RING_REGION_INDEX_TO_OFFSET(PKA_RING_REGION_CNTRS_IDX); > - region->addr = res->base + shim_base; > + region->addr = res->base; > region->size = res->size; > region->type = PKA_RING_RES_TYPE_CNTRS; > region->flags |= (PKA_RING_REGION_FLAG_MMAP | > @@ -238,7 +276,7 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) > /* map offset to the physical address */ > region->off = > PKA_RING_REGION_INDEX_TO_OFFSET(PKA_RING_REGION_MEM_IDX); > - region->addr = res->base + shim_base; > + region->addr = res->base; > region->size = res->size; > region->type = PKA_RING_RES_TYPE_MEM; > region->flags |= (PKA_RING_REGION_FLAG_MMAP | > @@ -714,30 +752,80 @@ static void pka_drv_destroy_class(void) > } > #endif > > +static void pka_drv_get_mem_res(struct pka_device *pka_dev, > + struct pka_dev_mem_res *mem_res, > + uint64_t wndw_ram_off_mask) > +{ > + enum pka_mem_res_idx acpi_mem_idx; > + > + acpi_mem_idx = PKA_ACPI_EIP154_IDX; > + mem_res->wndw_ram_off_mask = wndw_ram_off_mask; > + > + /* PKA EIP154 MMIO base address*/ > + mem_res->eip154_base = pka_dev->resource[acpi_mem_idx]->start; > + mem_res->eip154_size = pka_dev->resource[acpi_mem_idx]->end - > + mem_res->eip154_base + 1; > + acpi_mem_idx++; > + > + /* PKA window ram base address*/ > + mem_res->wndw_ram_base = pka_dev->resource[acpi_mem_idx]->start; > + mem_res->wndw_ram_size = pka_dev->resource[acpi_mem_idx]->end - > + mem_res->wndw_ram_base + 1; > + acpi_mem_idx++; > + > + /* PKA alternate window ram base address > + * Note: Here the size of all the alt window ram is same, depicted by > + * 'alt_wndw_ram_size' variable. All alt window ram resources are read > + * here even though not all of them are used currently. > + */ > + mem_res->alt_wndw_ram_0_base = pka_dev->resource[acpi_mem_idx]->start; > + mem_res->alt_wndw_ram_size = pka_dev->resource[acpi_mem_idx]->end - > + mem_res->alt_wndw_ram_0_base + 1; > + > + if (mem_res->alt_wndw_ram_size != PKA_WINDOW_RAM_REGION_SIZE) > + PKA_ERROR(PKA_DRIVER, > + "Alternate Window RAM size read from ACPI is incorrect.\n"); > + > + acpi_mem_idx++; > + > + mem_res->alt_wndw_ram_1_base = pka_dev->resource[acpi_mem_idx]->start; > + acpi_mem_idx++; > + > + mem_res->alt_wndw_ram_2_base = pka_dev->resource[acpi_mem_idx]->start; > + acpi_mem_idx++; > + > + mem_res->alt_wndw_ram_3_base = pka_dev->resource[acpi_mem_idx]->start; > + acpi_mem_idx++; > + > + /* PKA CSR base address*/ > + mem_res->csr_base = pka_dev->resource[acpi_mem_idx]->start; > + mem_res->csr_size = pka_dev->resource[acpi_mem_idx]->end - > + mem_res->csr_base + 1; > +} > + > /* > * Note that this function must be serialized because it calls > * 'pka_dev_register_shim' which manipulates common counters for > * pka devices. > */ > -static int pka_drv_register_device(struct pka_device *pka_dev) > +static int pka_drv_register_device(struct pka_device *pka_dev, > + uint64_t wndw_ram_off_mask) > { > uint32_t pka_shim_id; > - uint64_t pka_shim_base; > - uint64_t pka_shim_size; > uint8_t pka_shim_fw_id; > + struct pka_dev_mem_res mem_res; > > /* Register Shim */ > pka_shim_id = pka_dev->device_id; > - pka_shim_base = pka_dev->resource->start; > - pka_shim_size = pka_dev->resource->end - pka_shim_base; > pka_shim_fw_id = pka_dev->fw_id; > > - pka_dev->shim = pka_dev_register_shim(pka_shim_id, pka_shim_base, > - pka_shim_size, pka_shim_fw_id); > + pka_drv_get_mem_res(pka_dev, &mem_res, wndw_ram_off_mask); > + > + pka_dev->shim = pka_dev_register_shim(pka_shim_id, pka_shim_fw_id, > + &mem_res); > if (!pka_dev->shim) { > PKA_DEBUG(PKA_DRIVER, > - "failed to register shim id=%u, base=0x%llx, size=0x%llx\n", > - pka_shim_id, pka_shim_base, pka_shim_size); > + "failed to register shim id=%u\n", pka_shim_id); > return -EFAULT; > } > > @@ -830,9 +918,11 @@ static int pka_drv_probe_device(struct pka_info *info) > struct device_node *of_node = dev->of_node; > struct platform_device *pdev = to_platform_device(dev); > struct hwrng *trng; > - > - u8 revision; > + const struct acpi_device_id *aid; > + struct pka_drv_plat_info *plat_info; > + uint64_t wndw_ram_off_mask; > int ret; > + enum pka_mem_res_idx acpi_mem_idx; > > if (!info) > return -EINVAL; > @@ -858,8 +948,25 @@ static int pka_drv_probe_device(struct pka_info *info) > info->flag = PKA_DRIVER_FLAG_DEVICE; > mutex_init(&pka_dev->mutex); > > - pka_dev->resource = > - platform_get_resource(pdev, IORESOURCE_MEM, 0); > + for (acpi_mem_idx = PKA_ACPI_EIP154_IDX; > + acpi_mem_idx < PKA_DEVICE_RES_CNT; acpi_mem_idx++) { > + pka_dev->resource[acpi_mem_idx] = > + platform_get_resource(pdev, IORESOURCE_MEM, acpi_mem_idx); > + } > + > + /* Window ram offset mask is platform dependent */ > + aid = acpi_match_device(pka_drv_acpi_ids, dev); > + if (!aid) > + return -ENODEV; > + > + plat_info = (struct pka_drv_plat_info *)aid->driver_data; > + if (plat_info->type <= PKA_PLAT_TYPE_BF2) { > + wndw_ram_off_mask = PKA_WINDOW_RAM_OFFSET_MASK1; > + } else { > + PKA_ERROR(PKA_DRIVER, "Invalid platform type: %d\n", > + (int)plat_info->type); > + return -EINVAL; > + } > > /* Set interrupts */ > ret = platform_get_irq(pdev, 0); > @@ -881,33 +988,11 @@ static int pka_drv_probe_device(struct pka_info *info) > return ret; > } > > - /* > - * Retrieve the firmware identifier based on the device revision. > - * Note that old platform firmware of BF1 does not support the > - * "revision" property, thus set it by default. > - */ > - ret = device_property_read_u8(dev, "rev", &revision); > - if (ret < 0) > - revision = PKA_REVISION_1; > - > - switch (revision) { > - case PKA_REVISION_1: > - pka_dev->fw_id = PKA_FIRMWARE_IMAGE_0_ID; > - break; > - > - case PKA_REVISION_2: > - pka_dev->fw_id = PKA_FIRMWARE_IMAGE_1_ID; > - break; > - > - default: > - PKA_ERROR(PKA_DRIVER, > - "device %u revision %u is not supported\n", > - pka_dev->device_id, revision); > - return -EINVAL; > - } > + /* Firmware version */ > + pka_dev->fw_id = plat_info->fw_id; > > mutex_lock(&pka_drv_lock); > - ret = pka_drv_register_device(pka_dev); > + ret = pka_drv_register_device(pka_dev, wndw_ram_off_mask); > if (ret) { > PKA_DEBUG(PKA_DRIVER, "failed to register shim id=%u\n", > pka_dev->device_id); > @@ -1119,7 +1204,8 @@ static int pka_drv_acpi_probe(struct platform_device *pdev, > if (WARN_ON(!info->acpihid)) > return -EINVAL; > > - if (!strcmp(info->acpihid, pka_ring_acpihid)) { > + if (!strcmp(info->acpihid, pka_ring_acpihid_bf1) > + || !strcmp(info->acpihid, pka_ring_acpihid_bf2)) { > error = pka_drv_probe_ring_device(info); > if (error) { > PKA_DEBUG(PKA_DRIVER, > @@ -1130,7 +1216,8 @@ static int pka_drv_acpi_probe(struct platform_device *pdev, > PKA_DEBUG(PKA_DRIVER, "ring device %s probed\n", > pdev->name); > > - } else if (!strcmp(info->acpihid, pka_acpihid)) { > + } else if (!strcmp(info->acpihid, pka_acpihid_bf1) > + || !strcmp(info->acpihid, pka_acpihid_bf2)) { > error = pka_drv_probe_device(info); > if (error) { > PKA_DEBUG(PKA_DRIVER, > @@ -1262,12 +1349,6 @@ static const struct of_device_id pka_drv_match[] = { > > MODULE_DEVICE_TABLE(of, pka_drv_match); > > -static const struct acpi_device_id pka_drv_acpi_ids[] = { > - { PKA_DEVICE_ACPIHID, 0 }, > - { PKA_RING_DEVICE_ACPIHID, 0 }, > - {}, > -}; > - > MODULE_DEVICE_TABLE(acpi, pka_drv_acpi_ids); > > static struct platform_driver pka_drv = { >
On 19.02.21 20:22, Mahantesh Salimath wrote: > Buglink: https://bugs.launchpad.net/ubuntu/+source/linux-bluefield/+bug/1916274 > > * Read platform dependant memory addresses from ACPI and > remove these memory definitions from driver code. > > * Defining platform dependant memory addresses in ACPI > removes platform dependant code from driver. > It is also a better design as it will allow to > accomodate address changes with platform. > > Signed-off-by: Mahantesh Salimath <mahantesh@nvidia.com> > Reviewed-by: Khalil Blaiech <kblaiech@nvidia.com> > Singed-off-by: Mahantesh Salimath <mahantesh@nvidia.com> Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com> > --- > diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h > index becb45e..07cbcda 100644 > --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h > +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h > @@ -66,75 +66,74 @@ > > // EIP154 CSRS: > > -#define PKA_EIP154_ADDR 0x400000 > // Global Control Space CSR addresses/offsets. These are accessed from the > // ARM as 8 byte reads/writes however only the bottom 32 bits are implemented. > -#define PKA_CLOCK_SWITCH_ADDR (0x11C68 | PKA_EIP154_ADDR) > -#define PKA_CLK_FORCE_ADDR (0x11C80 | PKA_EIP154_ADDR) > -#define MODE_SELECTION_ADDR (0x11C88 | PKA_EIP154_ADDR) > -#define PKA_PROT_STATUS_ADDR (0x11C90 | PKA_EIP154_ADDR) > -#define PKA_OPTIONS_ADDR (0x11DF0 | PKA_EIP154_ADDR) > -#define PKA_VERSION_ADDR (0x11DF8 | PKA_EIP154_ADDR) > +#define PKA_CLOCK_SWITCH_ADDR 0x11C68 > +#define PKA_CLK_FORCE_ADDR 0x11C80 > +#define MODE_SELECTION_ADDR 0x11C88 > +#define PKA_PROT_STATUS_ADDR 0x11C90 > +#define PKA_OPTIONS_ADDR 0x11DF0 > +#define PKA_VERSION_ADDR 0x11DF8 > > // Advanced Interrupt Controller CSR addresses/offsets. These are accessed > // from the ARM as 8 byte reads/writes however only the bottom 32 bits are > // implemented. > -#define AIC_POL_CTRL_ADDR (0x11E00 | PKA_EIP154_ADDR) > -#define AIC_TYPE_CTRL_ADDR (0x11E08 | PKA_EIP154_ADDR) > -#define AIC_ENABLE_CTRL_ADDR (0x11E10 | PKA_EIP154_ADDR) > -#define AIC_RAW_STAT_ADDR (0x11E18 | PKA_EIP154_ADDR) > -#define AIC_ENABLE_SET_ADDR (0x11E18 | PKA_EIP154_ADDR) > -#define AIC_ENABLED_STAT_ADDR (0x11E20 | PKA_EIP154_ADDR) > -#define AIC_ACK_ADDR (0x11E20 | PKA_EIP154_ADDR) > -#define AIC_ENABLE_CLR_ADDR (0x11E28 | PKA_EIP154_ADDR) > -#define AIC_OPTIONS_ADDR (0x11E30 | PKA_EIP154_ADDR) > -#define AIC_VERSION_ADDR (0x11E38 | PKA_EIP154_ADDR) > +#define AIC_POL_CTRL_ADDR 0x11E00 > +#define AIC_TYPE_CTRL_ADDR 0x11E08 > +#define AIC_ENABLE_CTRL_ADDR 0x11E10 > +#define AIC_RAW_STAT_ADDR 0x11E18 > +#define AIC_ENABLE_SET_ADDR 0x11E18 > +#define AIC_ENABLED_STAT_ADDR 0x11E20 > +#define AIC_ACK_ADDR 0x11E20 > +#define AIC_ENABLE_CLR_ADDR 0x11E28 > +#define AIC_OPTIONS_ADDR 0x11E30 > +#define AIC_VERSION_ADDR 0x11E38 > > // The True Random Number Generator CSR addresses/offsets. These are accessed > // from the ARM as 8 byte reads/writes however only the bottom 32 bits are > // implemented. > -#define TRNG_OUTPUT_0_ADDR (0x12000 | PKA_EIP154_ADDR) > -#define TRNG_OUTPUT_1_ADDR (0x12008 | PKA_EIP154_ADDR) > -#define TRNG_OUTPUT_2_ADDR (0x12010 | PKA_EIP154_ADDR) > -#define TRNG_OUTPUT_3_ADDR (0x12018 | PKA_EIP154_ADDR) > -#define TRNG_STATUS_ADDR (0x12020 | PKA_EIP154_ADDR) > -#define TRNG_INTACK_ADDR (0x12020 | PKA_EIP154_ADDR) > -#define TRNG_CONTROL_ADDR (0x12028 | PKA_EIP154_ADDR) > -#define TRNG_CONFIG_ADDR (0x12030 | PKA_EIP154_ADDR) > -#define TRNG_ALARMCNT_ADDR (0x12038 | PKA_EIP154_ADDR) > -#define TRNG_FROENABLE_ADDR (0x12040 | PKA_EIP154_ADDR) > -#define TRNG_FRODETUNE_ADDR (0x12048 | PKA_EIP154_ADDR) > -#define TRNG_ALARMMASK_ADDR (0x12050 | PKA_EIP154_ADDR) > -#define TRNG_ALARMSTOP_ADDR (0x12058 | PKA_EIP154_ADDR) > -#define TRNG_BLOCKCNT_ADDR (0x120E8 | PKA_EIP154_ADDR) > -#define TRNG_OPTIONS_ADDR (0x120F0 | PKA_EIP154_ADDR) > +#define TRNG_OUTPUT_0_ADDR 0x12000 > +#define TRNG_OUTPUT_1_ADDR 0x12008 > +#define TRNG_OUTPUT_2_ADDR 0x12010 > +#define TRNG_OUTPUT_3_ADDR 0x12018 > +#define TRNG_STATUS_ADDR 0x12020 > +#define TRNG_INTACK_ADDR 0x12020 > +#define TRNG_CONTROL_ADDR 0x12028 > +#define TRNG_CONFIG_ADDR 0x12030 > +#define TRNG_ALARMCNT_ADDR 0x12038 > +#define TRNG_FROENABLE_ADDR 0x12040 > +#define TRNG_FRODETUNE_ADDR 0x12048 > +#define TRNG_ALARMMASK_ADDR 0x12050 > +#define TRNG_ALARMSTOP_ADDR 0x12058 > +#define TRNG_BLOCKCNT_ADDR 0x120E8 > +#define TRNG_OPTIONS_ADDR 0x120F0 > > // Control register address/offset. This is accessed from the ARM using 8 > // byte reads/writes however only the bottom 32 bits are implemented. > -#define PKA_MASTER_SEQ_CTRL_ADDR (0x27F90 | PKA_EIP154_ADDR) > +#define PKA_MASTER_SEQ_CTRL_ADDR 0x27F90 > > // Ring CSRs: These are all accessed from the ARM using 8 byte reads/writes > // however only the bottom 32 bits are implemented. > > // Ring 0 CSRS > -#define COMMAND_COUNT_0_ADDR (0x80080 | PKA_EIP154_ADDR) > -#define RESULT_COUNT_0_ADDR (0x80088 | PKA_EIP154_ADDR) > -#define IRQ_THRESH_0_ADDR (0x80090 | PKA_EIP154_ADDR) > +#define COMMAND_COUNT_0_ADDR 0x80080 > +#define RESULT_COUNT_0_ADDR 0x80088 > +#define IRQ_THRESH_0_ADDR 0x80090 > > // Ring 1 CSRS: > -#define COMMAND_COUNT_1_ADDR (0x90080 | PKA_EIP154_ADDR) > -#define RESULT_COUNT_1_ADDR (0x90088 | PKA_EIP154_ADDR) > -#define IRQ_THRESH_1_ADDR (0x90090 | PKA_EIP154_ADDR) > +#define COMMAND_COUNT_1_ADDR 0x90080 > +#define RESULT_COUNT_1_ADDR 0x90088 > +#define IRQ_THRESH_1_ADDR 0x90090 > > // Ring 2 CSRS: > -#define COMMAND_COUNT_2_ADDR (0xA0080 | PKA_EIP154_ADDR) > -#define RESULT_COUNT_2_ADDR (0xA0088 | PKA_EIP154_ADDR) > -#define IRQ_THRESH_2_ADDR (0xA0090 | PKA_EIP154_ADDR) > +#define COMMAND_COUNT_2_ADDR 0xA0080 > +#define RESULT_COUNT_2_ADDR 0xA0088 > +#define IRQ_THRESH_2_ADDR 0xA0090 > > // Ring 3 CSRS: > -#define COMMAND_COUNT_3_ADDR (0xB0080 | PKA_EIP154_ADDR) > -#define RESULT_COUNT_3_ADDR (0xB0088 | PKA_EIP154_ADDR) > -#define IRQ_THRESH_3_ADDR (0xB0090 | PKA_EIP154_ADDR) > +#define COMMAND_COUNT_3_ADDR 0xB0080 > +#define RESULT_COUNT_3_ADDR 0xB0088 > +#define IRQ_THRESH_3_ADDR 0xB0090 > > // EIP154 RAM regions: Note that the FARM_PROG_RAM_X address range overlaps > // with the FARM_DATA_RAM_X and FARM_DATA_RAM_X_EXT address ranges. This > @@ -164,115 +163,100 @@ > // PKA Farm Data RAM extension size : 4KB --> 8KB > // PKA Farm Program RAM size : 8KB --> 16KB > // > -#define PKA_BUFFER_RAM_BASE (0x00000 | PKA_EIP154_ADDR) > +#define PKA_BUFFER_RAM_BASE 0x00000 > #define PKA_BUFFER_RAM_SIZE MEM_SIZE_16KB // 0x00000...0x03FFF > > -#define PKA_SECURE_RAM_BASE (0x20000 | PKA_EIP154_ADDR) > +#define PKA_SECURE_RAM_BASE 0x20000 > #define PKA_SECURE_RAM_SIZE MEM_SIZE_16KB // 0x20000...0x23FFF > > -#define PKA_MASTER_PROG_RAM_BASE (0x30000 | PKA_EIP154_ADDR) > +#define PKA_MASTER_PROG_RAM_BASE 0x30000 > #define PKA_MASTER_PROG_RAM_SIZE MEM_SIZE_64KB // 0x30000...0x3FFFF > > -#define FARM_DATA_RAM_0_BASE (0x40000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_0_BASE 0x40000 > #define FARM_DATA_RAM_0_SIZE MEM_SIZE_8KB // 0x40000...0x41FFF > -#define FARM_DATA_RAM_0_EXT_BASE (0x42000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_0_EXT_BASE 0x42000 > #define FARM_DATA_RAM_0_EXT_SIZE MEM_SIZE_8KB // 0x42000...0x43FFF > -#define FARM_PROG_RAM_0_BASE (0x40000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_0_BASE 0x40000 > #define FARM_PROG_RAM_0_SIZE MEM_SIZE_16KB // 0x40000...0x43FFF > -#define FARM_DATA_RAM_1_BASE (0x44000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_1_BASE 0x44000 > #define FARM_DATA_RAM_1_SIZE MEM_SIZE_8KB // 0x44000...0x45FFF > -#define FARM_DATA_RAM_1_EXT_BASE (0x46000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_1_EXT_BASE 0x46000 > #define FARM_DATA_RAM_1_EXT_SIZE MEM_SIZE_8KB // 0x46000...0x47FFF > -#define FARM_PROG_RAM_1_BASE (0x44000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_1_BASE 0x44000 > #define FARM_PROG_RAM_1_SIZE MEM_SIZE_16KB // 0x44000...0x47FFF > -#define FARM_DATA_RAM_2_BASE (0x48000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_2_BASE 0x48000 > #define FARM_DATA_RAM_2_SIZE MEM_SIZE_8KB // 0x48000...0x49FFF > -#define FARM_DATA_RAM_2_EXT_BASE (0x4A000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_2_EXT_BASE 0x4A000 > #define FARM_DATA_RAM_2_EXT_SIZE MEM_SIZE_8KB // 0x4A000...0x4BFFF > -#define FARM_PROG_RAM_2_BASE (0x48000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_2_BASE 0x48000 > #define FARM_PROG_RAM_2_SIZE MEM_SIZE_16KB // 0x48000...0x4BFFF > -#define FARM_DATA_RAM_3_BASE (0x4C000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_3_BASE 0x4C000 > #define FARM_DATA_RAM_3_SIZE MEM_SIZE_8KB // 0x4C000...0x4DFFF > -#define FARM_DATA_RAM_3_EXT_BASE (0x4E000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_3_EXT_BASE 0x4E000 > #define FARM_DATA_RAM_3_EXT_SIZE MEM_SIZE_8KB // 0x4E000...0x4FFFF > -#define FARM_PROG_RAM_3_BASE (0x4C000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_3_BASE 0x4C000 > #define FARM_PROG_RAM_3_SIZE MEM_SIZE_16KB // 0x4C000...0x4FFFF > -#define FARM_DATA_RAM_4_BASE (0x50000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_4_BASE 0x50000 > #define FARM_DATA_RAM_4_SIZE MEM_SIZE_8KB // 0x50000...0x51FFF > -#define FARM_DATA_RAM_4_EXT_BASE (0x52000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_4_EXT_BASE 0x52000 > #define FARM_DATA_RAM_4_EXT_SIZE MEM_SIZE_8KB // 0x52000...0x53FFF > -#define FARM_PROG_RAM_4_BASE (0x50000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_4_BASE 0x50000 > #define FARM_PROG_RAM_4_SIZE MEM_SIZE_16KB // 0x50000...0x53FFF > -#define FARM_DATA_RAM_5_BASE (0x54000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_5_BASE 0x54000 > #define FARM_DATA_RAM_5_SIZE MEM_SIZE_8KB // 0x54000...0x55FFF > -#define FARM_DATA_RAM_5_EXT_BASE (0x56000 | PKA_EIP154_ADDR) > +#define FARM_DATA_RAM_5_EXT_BASE 0x56000 > #define FARM_DATA_RAM_5_EXT_SIZE MEM_SIZE_8KB // 0x56000...0x57FFF > -#define FARM_PROG_RAM_5_BASE (0x54000 | PKA_EIP154_ADDR) > +#define FARM_PROG_RAM_5_BASE 0x54000 > #define FARM_PROG_RAM_5_SIZE MEM_SIZE_16KB // 0x54000...0x57FFF > > // PKA Buffer RAM offsets. These are NOT real CSR's but instead are > // specific offset/addresses within the EIP154 PKA_BUFFER_RAM. > > // Ring 0: > -#define RING_CMMD_BASE_0_ADDR (0x00000 | PKA_EIP154_ADDR) > -#define RING_RSLT_BASE_0_ADDR (0x00010 | PKA_EIP154_ADDR) > -#define RING_SIZE_TYPE_0_ADDR (0x00020 | PKA_EIP154_ADDR) > -#define RING_RW_PTRS_0_ADDR (0x00028 | PKA_EIP154_ADDR) > -#define RING_RW_STAT_0_ADDR (0x00030 | PKA_EIP154_ADDR) > +#define RING_CMMD_BASE_0_ADDR 0x00000 > +#define RING_RSLT_BASE_0_ADDR 0x00010 > +#define RING_SIZE_TYPE_0_ADDR 0x00020 > +#define RING_RW_PTRS_0_ADDR 0x00028 > +#define RING_RW_STAT_0_ADDR 0x00030 > > // Ring 1 > -#define RING_CMMD_BASE_1_ADDR (0x00040 | PKA_EIP154_ADDR) > -#define RING_RSLT_BASE_1_ADDR (0x00050 | PKA_EIP154_ADDR) > -#define RING_SIZE_TYPE_1_ADDR (0x00060 | PKA_EIP154_ADDR) > -#define RING_RW_PTRS_1_ADDR (0x00068 | PKA_EIP154_ADDR) > -#define RING_RW_STAT_1_ADDR (0x00070 | PKA_EIP154_ADDR) > +#define RING_CMMD_BASE_1_ADDR 0x00040 > +#define RING_RSLT_BASE_1_ADDR 0x00050 > +#define RING_SIZE_TYPE_1_ADDR 0x00060 > +#define RING_RW_PTRS_1_ADDR 0x00068 > +#define RING_RW_STAT_1_ADDR 0x00070 > > // Ring 2 > -#define RING_CMMD_BASE_2_ADDR (0x00080 | PKA_EIP154_ADDR) > -#define RING_RSLT_BASE_2_ADDR (0x00090 | PKA_EIP154_ADDR) > -#define RING_SIZE_TYPE_2_ADDR (0x000A0 | PKA_EIP154_ADDR) > -#define RING_RW_PTRS_2_ADDR (0x000A8 | PKA_EIP154_ADDR) > -#define RING_RW_STAT_2_ADDR (0x000B0 | PKA_EIP154_ADDR) > +#define RING_CMMD_BASE_2_ADDR 0x00080 > +#define RING_RSLT_BASE_2_ADDR 0x00090 > +#define RING_SIZE_TYPE_2_ADDR 0x000A0 > +#define RING_RW_PTRS_2_ADDR 0x000A8 > +#define RING_RW_STAT_2_ADDR 0x000B0 > > // Ring 3 > -#define RING_CMMD_BASE_3_ADDR (0x000C0 | PKA_EIP154_ADDR) > -#define RING_RSLT_BASE_3_ADDR (0x000D0 | PKA_EIP154_ADDR) > -#define RING_SIZE_TYPE_3_ADDR (0x000E0 | PKA_EIP154_ADDR) > -#define RING_RW_PTRS_3_ADDR (0x000E8 | PKA_EIP154_ADDR) > -#define RING_RW_STAT_3_ADDR (0x000F0 | PKA_EIP154_ADDR) > +#define RING_CMMD_BASE_3_ADDR 0x000C0 > +#define RING_RSLT_BASE_3_ADDR 0x000D0 > +#define RING_SIZE_TYPE_3_ADDR 0x000E0 > +#define RING_RW_PTRS_3_ADDR 0x000E8 > +#define RING_RW_STAT_3_ADDR 0x000F0 > > // Ring Options > -#define PKA_RING_OPTIONS_ADDR (0x07FF8 | PKA_EIP154_ADDR) > +#define PKA_RING_OPTIONS_ADDR 0x07FF8 > > -// Note the registers/memory below include MiCA specific PKA Control/Status > -// registers and the 64K RAM's that the EIP-154 calls Host Memory. > - > -// Note that Window RAM size is 64K however only the low 16K can be accessed. > -#define PKA_WINDOW_RAM_BASE 0x500000 > -#define PKA_WINDOW_RAM_SIZE MEM_SIZE_64KB > +// Alternate Window RAM size > #define PKA_WINDOW_RAM_REGION_SIZE MEM_SIZE_16KB > > -#define PKA_WINDOW_RAM_REGION_0_BASE 0x600000 > -#define PKA_WINDOW_RAM_REGION_0_SIZE PKA_WINDOW_RAM_REGION_SIZE > -#define PKA_WINDOW_RAM_REGION_1_BASE 0x610000 > -#define PKA_WINDOW_RAM_REGION_1_SIZE PKA_WINDOW_RAM_REGION_SIZE > -#define PKA_WINDOW_RAM_REGION_2_BASE 0x620000 > -#define PKA_WINDOW_RAM_REGION_2_SIZE PKA_WINDOW_RAM_REGION_SIZE > -#define PKA_WINDOW_RAM_REGION_3_BASE 0x630000 > -#define PKA_WINDOW_RAM_REGION_3_SIZE PKA_WINDOW_RAM_REGION_SIZE > - > // Currently, we do not use these MiCA specific CSRs. > -#define PKI_EXT_CSR_START_ADDR 0x510000 > > // The PKI (not EIP154) CSR address/offsets: These are all addressed as > // 8-byte registers. > -#define PKA_INT_MASK_ADDR (0x00 | PKI_EXT_CSR_START_ADDR) > -#define PKA_INT_MASK_SET_ADDR (0x08 | PKI_EXT_CSR_START_ADDR) > -#define PKA_INT_MASK_RESET_ADDR (0x10 | PKI_EXT_CSR_START_ADDR) > -#define PKA_ZEROIZE_ADDR (0x40 | PKI_EXT_CSR_START_ADDR) > -#define TST_FRO_ADDR (0x50 | PKI_EXT_CSR_START_ADDR) > -#define FRO_COUNT_ADDR (0x58 | PKI_EXT_CSR_START_ADDR) > -#define PKA_PARITY_CTL_ADDR (0x60 | PKI_EXT_CSR_START_ADDR) > -#define PKA_PARITY_STAT_ADDR (0x68 | PKI_EXT_CSR_START_ADDR) > +#define PKA_INT_MASK_ADDR 0x00 > +#define PKA_INT_MASK_SET_ADDR 0x08 > +#define PKA_INT_MASK_RESET_ADDR 0x10 > +#define PKA_ZEROIZE_ADDR 0x40 > +#define TST_FRO_ADDR 0x50 > +#define FRO_COUNT_ADDR 0x58 > +#define PKA_PARITY_CTL_ADDR 0x60 > +#define PKA_PARITY_STAT_ADDR 0x68 > > #endif // __PKA_ADDRS_H__ > diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h > index 4cda85d..b590477 100644 > --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h > +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h > @@ -53,13 +53,10 @@ > // and ring spacing. > #define PKA_RING_WORDS_ADDR PKA_BUFFER_RAM_BASE > #define PKA_RING_CNTRS_ADDR COMMAND_COUNT_0_ADDR > -#define PKA_RING_MEM_0_BASE PKA_WINDOW_RAM_BASE > -#define PKA_RING_MEM_1_BASE PKA_WINDOW_RAM_REGION_0_BASE > > #define PKA_RING_WORDS_SIZE 0x40 // 64 bytes > #define PKA_RING_CNTRS_SIZE 0x20 // 32 bytes (3 count registers) > -#define PKA_RING_MEM_0_SIZE PKA_WINDOW_RAM_REGION_SIZE > -#define PKA_RING_MEM_1_SIZE PKA_WINDOW_RAM_REGION_SIZE > +#define PKA_RING_MEM_SIZE 0x4000 // 16K bytes > > #define PKA_RING_WORDS_SPACING 0x40 // 64 bytes > #define PKA_RING_CNTRS_SPACING 0x10000 // 64K bytes > @@ -75,11 +72,18 @@ > #define PKA_WINDOW_RAM_RING_MEM_SIZE 0x0800 // 2KB > #define PKA_WINDOW_RAM_DATA_MEM_SIZE 0x3800 // 14KB > > +// Offset mask, common to both Window and Alternate Window RAM. > +#define PKA_WINDOW_RAM_OFFSET_MASK1 0x730000 > + > // Macro for mapping PKA Ring address into Window RAM address. It converts the > // ring address, either physical address or virtual address, to valid address > -// into the Window RAM. This is done assuming the Window RAM base and size. > -#define PKA_RING_MEM_ADDR(addr, size) \ > - (PKA_WINDOW_RAM_BASE | (((addr) & 0xffff) | \ > +// into the Window RAM. This is done assuming the Window RAM base, size and > +// mask. Here, base is the actual physical address of the Window RAM, with the > +// help of mask it is reduced to Window RAM offset within that PKA block. > +// Further, with the help of addr and size, we arrive at the Window RAM > +// offset address for a PKA Ring within the given Window RAM. > +#define PKA_RING_MEM_ADDR(base, mask, addr, size) \ > + ((base & mask) | (((addr) & 0xffff) | \ > ((((addr) & ~((size) - 1)) & 0xf0000) >> 2))) > > // PKA Master Sequencer Control/Status Register > diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c > index 4539bae..8e4141b 100644 > --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c > +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c > @@ -175,7 +175,7 @@ static int pka_dev_set_resource_config(pka_dev_shim_t *shim, > res_ptr->base = res_base; > > if (res_type == PKA_DEV_RES_TYPE_MEM) > - res_ptr->base = shim->base + res_base; > + res_ptr->base = shim->mem_res.eip154_base + res_base; > > res_ptr->size = res_size; > res_ptr->type = res_type; > @@ -267,7 +267,6 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, > uint32_t ring_cntrs_off; > uint32_t ring_mem_off; > uint32_t ring_mem_base; > - uint32_t ring_mem_size; > > uint32_t shim_ring_id; > uint8_t window_ram_split; > @@ -294,7 +293,8 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, > // Configure ring information control/status words resource > ring_info_words_ptr = &ring->resources.info_words; > ring_words_off = shim_ring_id * PKA_RING_WORDS_SPACING; > - ring_info_words_ptr->base = ring_words_off + PKA_RING_WORDS_ADDR; > + ring_info_words_ptr->base = ring_words_off + shim->mem_res.eip154_base + > + PKA_RING_WORDS_ADDR; > ring_info_words_ptr->size = PKA_RING_WORDS_SIZE; > ring_info_words_ptr->type = PKA_DEV_RES_TYPE_MEM; > ring_info_words_ptr->status = PKA_DEV_RES_STATUS_UNMAPPED; > @@ -303,7 +303,8 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, > // Configure ring counters registers resource > ring_counters_ptr = &ring->resources.counters; > ring_cntrs_off = shim_ring_id * PKA_RING_CNTRS_SPACING; > - ring_counters_ptr->base = ring_cntrs_off + PKA_RING_CNTRS_ADDR; > + ring_counters_ptr->base = ring_cntrs_off + shim->mem_res.eip154_base + > + PKA_RING_CNTRS_ADDR; > ring_counters_ptr->size = PKA_RING_CNTRS_SIZE; > ring_counters_ptr->type = PKA_DEV_RES_TYPE_REG; > ring_counters_ptr->status = PKA_DEV_RES_STATUS_UNMAPPED; > @@ -314,19 +315,17 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, > if (window_ram_split == PKA_SHIM_WINDOW_RAM_SPLIT_ENABLED) > { > ring_mem_off = shim_ring_id * PKA_RING_MEM_1_SPACING; > - ring_mem_base = ring_mem_off + PKA_RING_MEM_1_BASE; > - ring_mem_size = PKA_RING_MEM_1_SIZE; > + ring_mem_base = ring_mem_off + shim->mem_res.alt_wndw_ram_0_base; > } > else > { > ring_mem_off = shim_ring_id * PKA_RING_MEM_0_SPACING; > - ring_mem_base = ring_mem_off + PKA_RING_MEM_0_BASE; > - ring_mem_size = PKA_RING_MEM_0_SIZE; > + ring_mem_base = ring_mem_off + shim->mem_res.wndw_ram_base; > } > > ring_window_ram_ptr = &ring->resources.window_ram; > ring_window_ram_ptr->base = ring_mem_base; > - ring_window_ram_ptr->size = ring_mem_size; > + ring_window_ram_ptr->size = PKA_RING_MEM_SIZE; > ring_window_ram_ptr->type = PKA_DEV_RES_TYPE_MEM; > ring_window_ram_ptr->status = PKA_DEV_RES_STATUS_UNMAPPED; > ring_window_ram_ptr->name = "PKA_RING_WINDOW"; > @@ -474,9 +473,11 @@ static int pka_dev_partition_mem(pka_dev_ring_t *ring) > rslt_desc_ring_base = ring_mem_base + cmd_desc_ring_size; > > cmd_desc_ring_base = > - PKA_RING_MEM_ADDR(cmd_desc_ring_base, window_ram_size); > + PKA_RING_MEM_ADDR(window_ram_base, shim->mem_res.wndw_ram_off_mask, > + cmd_desc_ring_base, window_ram_size); > rslt_desc_ring_base = > - PKA_RING_MEM_ADDR(rslt_desc_ring_base, window_ram_size); > + PKA_RING_MEM_ADDR(window_ram_base, shim->mem_res.wndw_ram_off_mask, > + rslt_desc_ring_base, window_ram_size); > > ring_info = ring->ring_info; > // Fill ring information. > @@ -629,7 +630,7 @@ static int pka_dev_set_ring_info(pka_dev_ring_t *ring) > // Create shim. Set shim parameters and configure shim resources. > // It returns 0 on success, a negative error code on failure. > static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > - uint64_t shim_base, uint64_t shim_size, uint8_t split) > + uint8_t split, struct pka_dev_mem_res *mem_res) > { > int ret = 0; > > @@ -652,8 +653,7 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > } > > shim->shim_id = shim_id; > - shim->base = shim_base; > - shim->size = shim_size; > + shim->mem_res = *mem_res; > > if (split) > shim->window_ram_split = PKA_SHIM_WINDOW_RAM_SPLIT_ENABLED; > @@ -674,10 +674,10 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device Buffer RAM config > ret = pka_dev_set_resource_config(shim, &shim->resources.buffer_ram, > - PKA_BUFFER_RAM_BASE, > - PKA_BUFFER_RAM_SIZE, > - PKA_DEV_RES_TYPE_MEM, > - "PKA_BUFFER_RAM"); > + PKA_BUFFER_RAM_BASE, > + PKA_BUFFER_RAM_SIZE, > + PKA_DEV_RES_TYPE_MEM, > + "PKA_BUFFER_RAM"); > if (ret) > { > PKA_ERROR(PKA_DEV, "unable to set Buffer RAM config\n"); > @@ -686,10 +686,10 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device Master Program RAM config > ret = pka_dev_set_resource_config(shim, &shim->resources.master_prog_ram, > - PKA_MASTER_PROG_RAM_BASE, > - PKA_MASTER_PROG_RAM_SIZE, > - PKA_DEV_RES_TYPE_MEM, > - "PKA_MASTER_PROG_RAM"); > + PKA_MASTER_PROG_RAM_BASE, > + PKA_MASTER_PROG_RAM_SIZE, > + PKA_DEV_RES_TYPE_MEM, > + "PKA_MASTER_PROG_RAM"); > if (ret) > { > PKA_ERROR(PKA_DEV, "unable to set Master Program RAM config\n"); > @@ -698,12 +698,12 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device Master Controller register > reg_size = PAGE_SIZE; > - reg_base = pka_dev_get_register_base(shim->base, > - PKA_MASTER_SEQ_CTRL_ADDR); > + reg_base = pka_dev_get_register_base(shim->mem_res.eip154_base, > + PKA_MASTER_SEQ_CTRL_ADDR); > ret = pka_dev_set_resource_config(shim, &shim->resources.master_seq_ctrl, > - reg_base, reg_size, > - PKA_DEV_RES_TYPE_REG, > - "PKA_MASTER_SEQ_CTRL"); > + reg_base, reg_size, > + PKA_DEV_RES_TYPE_REG, > + "PKA_MASTER_SEQ_CTRL"); > if (ret) > { > PKA_ERROR(PKA_DEV, "unable to set Master Controller register " > @@ -713,8 +713,8 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device AIC registers > reg_size = PAGE_SIZE; > - reg_base = pka_dev_get_register_base(shim->base, > - AIC_POL_CTRL_ADDR); > + reg_base = pka_dev_get_register_base(shim->mem_res.eip154_base, > + AIC_POL_CTRL_ADDR); > ret = pka_dev_set_resource_config(shim, &shim->resources.aic_csr, > reg_base, reg_size, > PKA_DEV_RES_TYPE_REG, > @@ -727,8 +727,8 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device TRNG registers > reg_size = PAGE_SIZE; > - reg_base = pka_dev_get_register_base(shim->base, > - TRNG_OUTPUT_0_ADDR); > + reg_base = pka_dev_get_register_base(shim->mem_res.eip154_base, > + TRNG_OUTPUT_0_ADDR); > ret = pka_dev_set_resource_config(shim, &shim->resources.trng_csr, > reg_base, reg_size, > PKA_DEV_RES_TYPE_REG, > @@ -741,8 +741,8 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, > > // Set PKA device 'glue' logic registers > reg_size = PAGE_SIZE; > - reg_base = pka_dev_get_register_base(shim->base, > - PKA_INT_MASK_ADDR); > + reg_base = pka_dev_get_register_base(shim->mem_res.csr_base, > + PKA_INT_MASK_ADDR); > ret = pka_dev_set_resource_config(shim, &shim->resources.ext_csr, > reg_base, reg_size, > PKA_DEV_RES_TYPE_REG, > @@ -1433,16 +1433,14 @@ int pka_dev_unregister_ring(pka_dev_ring_t *ring) > } > > static pka_dev_shim_t *__pka_dev_register_shim(uint32_t shim_id, > - uint64_t shim_base, > - uint64_t shim_size) > + struct pka_dev_mem_res *mem_res) > { > pka_dev_shim_t *shim; > > uint8_t split; > int ret = 0; > > - PKA_DEBUG(PKA_DEV, "register shim id=%u, start=0x%llx end=0x%llx\n", > - shim_id, shim_base, shim_base + shim_size); > + PKA_DEBUG(PKA_DEV, "register shim id=%u\n", shim_id); > > shim = kzalloc(sizeof(pka_dev_shim_t), GFP_KERNEL); > if (!shim) > @@ -1456,7 +1454,7 @@ static pka_dev_shim_t *__pka_dev_register_shim(uint32_t shim_id, > split = PKA_SPLIT_WINDOW_RAM_MODE; > > // Create PKA shim > - ret = pka_dev_create_shim(shim, shim_id, shim_base, shim_size, split); > + ret = pka_dev_create_shim(shim, shim_id, split, mem_res); > if (ret) > { > PKA_ERROR(PKA_DEV, "failed to create shim %u\n", shim_id); > @@ -1479,14 +1477,14 @@ static pka_dev_shim_t *__pka_dev_register_shim(uint32_t shim_id, > return shim; > } > > -pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint64_t shim_base, > - uint64_t shim_size, uint8_t shim_fw_id) > +pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint8_t shim_fw_id, > + struct pka_dev_mem_res *mem_res) > { > pka_dev_shim_t *shim; > > pka_firmware_set_id(shim_fw_id); > > - shim = __pka_dev_register_shim(shim_id, shim_base, shim_size); > + shim = __pka_dev_register_shim(shim_id, mem_res); > if (shim) > { > pka_gbl_config.dev_shims[shim->shim_id] = shim; > diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h > index 5a6cc8fd..b42ab5d 100644 > --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h > +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h > @@ -159,11 +159,30 @@ typedef struct > uint8_t res_cnt; > } pka_dev_gbl_shim_res_info_t; > > +struct pka_dev_mem_res > +{ > + uint64_t eip154_base; ///< base address for eip154 mmio registers > + uint64_t eip154_size; ///< eip154 mmio register region size > + > + uint64_t wndw_ram_off_mask; ///< common offset mask for alt window ram and window ram > + uint64_t wndw_ram_base; ///< base address for window ram > + uint64_t wndw_ram_size; ///< window ram region size > + > + uint64_t alt_wndw_ram_0_base; ///< base address for alternate window ram 0 > + uint64_t alt_wndw_ram_1_base; ///< base address for alternate window ram 1 > + uint64_t alt_wndw_ram_2_base; ///< base address for alternate window ram 2 > + uint64_t alt_wndw_ram_3_base; ///< base address for alternate window ram 3 > + uint64_t alt_wndw_ram_size; ///< alternate window ram regions size > + > + uint64_t csr_base; ///< base address for csr registers > + uint64_t csr_size; ///< csr area size > +}; > + > + > /// PKA Shim structure > struct pka_dev_shim_s > { > - uint64_t base; ///< shim base address > - uint64_t size; ///< shim io memory size > + struct pka_dev_mem_res mem_res; > > uint64_t trng_err_cycle; ///< TRNG error cycle > > @@ -252,8 +271,8 @@ int pka_dev_unregister_ring(pka_dev_ring_t *ring); > > /// Register PKA IO block. This function initializes a shim and configures its > /// related resources, and returns a pointer to that ring. > -pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint64_t shim_base, > - uint64_t shim_size, uint8_t shim_fw_id); > +pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint8_t shim_fw_id, > + struct pka_dev_mem_res *mem_res); > > /// Unregister PKA IO block > int pka_dev_unregister_shim(pka_dev_shim_t *shim); > diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c > index f93efb66..2290e72 100644 > --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c > +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c > @@ -28,11 +28,30 @@ > #define PKA_DEVICE_COMPAT "mlx,mlxbf-pka" > #define PKA_RING_DEVICE_COMPAT "mlx,mlxbf-pka-ring" > > -#define PKA_DEVICE_ACPIHID "MLNXBF10" > -#define PKA_RING_DEVICE_ACPIHID "MLNXBF11" > +#define PKA_DEVICE_ACPIHID_BF1 "MLNXBF10" > +#define PKA_RING_DEVICE_ACPIHID_BF1 "MLNXBF11" > + > +#define PKA_DEVICE_ACPIHID_BF2 "MLNXBF20" > +#define PKA_RING_DEVICE_ACPIHID_BF2 "MLNXBF21" > > #define PKA_DEVICE_ACCESS_MODE 0666 > > +#define PKA_DEVICE_RES_CNT 7 > +enum pka_mem_res_idx { > + PKA_ACPI_EIP154_IDX = 0, > + PKA_ACPI_WNDW_RAM_IDX, > + PKA_ACPI_ALT_WNDW_RAM_0_IDX, > + PKA_ACPI_ALT_WNDW_RAM_1_IDX, > + PKA_ACPI_ALT_WNDW_RAM_2_IDX, > + PKA_ACPI_ALT_WNDW_RAM_3_IDX, > + PKA_ACPI_CSR_IDX > +}; > + > +enum pka_plat_type { > + PKA_PLAT_TYPE_BF1 = 0, /* Platform type Bluefield-1 */ > + PKA_PLAT_TYPE_BF2 /* Platform type Bluefield-2 */ > +}; > + > static DEFINE_MUTEX(pka_drv_lock); > > static uint32_t pka_device_cnt; > @@ -41,8 +60,35 @@ static uint32_t pka_ring_device_cnt; > const char pka_compat[] = PKA_DEVICE_COMPAT; > const char pka_ring_compat[] = PKA_RING_DEVICE_COMPAT; > > -const char pka_acpihid[] = PKA_DEVICE_ACPIHID; > -const char pka_ring_acpihid[] = PKA_RING_DEVICE_ACPIHID; > +const char pka_acpihid_bf1[] = PKA_DEVICE_ACPIHID_BF1; > +const char pka_ring_acpihid_bf1[] = PKA_RING_DEVICE_ACPIHID_BF1; > + > +const char pka_acpihid_bf2[] = PKA_DEVICE_ACPIHID_BF2; > +const char pka_ring_acpihid_bf2[] = PKA_RING_DEVICE_ACPIHID_BF2; > + > +struct pka_drv_plat_info { > + enum pka_plat_type type; > + uint8_t fw_id; > +}; > + > +static struct pka_drv_plat_info pka_drv_plat[] = { > + [PKA_PLAT_TYPE_BF1] = { > + .type = PKA_PLAT_TYPE_BF1, > + .fw_id = PKA_FIRMWARE_IMAGE_0_ID > + }, > + [PKA_PLAT_TYPE_BF2] = { > + .type = PKA_PLAT_TYPE_BF2, > + .fw_id = PKA_FIRMWARE_IMAGE_1_ID > + } > +}; > + > +static const struct acpi_device_id pka_drv_acpi_ids[] = { > + { PKA_DEVICE_ACPIHID_BF1, (kernel_ulong_t)&pka_drv_plat[PKA_PLAT_TYPE_BF1] }, > + { PKA_RING_DEVICE_ACPIHID_BF1, 0 }, > + { PKA_DEVICE_ACPIHID_BF2, (kernel_ulong_t)&pka_drv_plat[PKA_PLAT_TYPE_BF2] }, > + { PKA_RING_DEVICE_ACPIHID_BF2, 0 }, > + {}, > +}; > > struct pka_info { > struct device *dev; /* the device this info belongs to */ > @@ -59,11 +105,6 @@ struct pka_info { > #define PKA_DRIVER_FLAG_RING_DEVICE 1 > #define PKA_DRIVER_FLAG_DEVICE 2 > > -enum { > - PKA_REVISION_1 = 1, > - PKA_REVISION_2, > -}; > - > struct pka_platdata { > struct platform_device *pdev; > struct pka_info *info; > @@ -138,7 +179,7 @@ struct pka_device { > uint32_t device_id; > uint8_t fw_id; /* firmware identifier */ > struct mutex mutex; > - struct resource *resource; > + struct resource *resource[PKA_DEVICE_RES_CNT]; > pka_dev_shim_t *shim; > long irq; /* interrupt number */ > struct hwrng rng; > @@ -189,7 +230,6 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) > struct pka_ring_region *region; > pka_dev_ring_t *ring; > pka_dev_res_t *res; > - uint64_t shim_base; > uint32_t num_regions; > > ring = ring_dev->ring; > @@ -204,15 +244,13 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) > if (!ring_dev->regions) > return -ENOMEM; > > - shim_base = ring->shim->base; > - > /* Information words region */ > res = &ring->resources.info_words; > region = &ring_dev->regions[PKA_RING_REGION_WORDS_IDX]; > /* map offset to the physical address */ > region->off = > PKA_RING_REGION_INDEX_TO_OFFSET(PKA_RING_REGION_WORDS_IDX); > - region->addr = res->base + shim_base; > + region->addr = res->base; > region->size = res->size; > region->type = PKA_RING_RES_TYPE_WORDS; > region->flags |= (PKA_RING_REGION_FLAG_MMAP | > @@ -225,7 +263,7 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) > /* map offset to the physical address */ > region->off = > PKA_RING_REGION_INDEX_TO_OFFSET(PKA_RING_REGION_CNTRS_IDX); > - region->addr = res->base + shim_base; > + region->addr = res->base; > region->size = res->size; > region->type = PKA_RING_RES_TYPE_CNTRS; > region->flags |= (PKA_RING_REGION_FLAG_MMAP | > @@ -238,7 +276,7 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) > /* map offset to the physical address */ > region->off = > PKA_RING_REGION_INDEX_TO_OFFSET(PKA_RING_REGION_MEM_IDX); > - region->addr = res->base + shim_base; > + region->addr = res->base; > region->size = res->size; > region->type = PKA_RING_RES_TYPE_MEM; > region->flags |= (PKA_RING_REGION_FLAG_MMAP | > @@ -714,30 +752,80 @@ static void pka_drv_destroy_class(void) > } > #endif > > +static void pka_drv_get_mem_res(struct pka_device *pka_dev, > + struct pka_dev_mem_res *mem_res, > + uint64_t wndw_ram_off_mask) > +{ > + enum pka_mem_res_idx acpi_mem_idx; > + > + acpi_mem_idx = PKA_ACPI_EIP154_IDX; > + mem_res->wndw_ram_off_mask = wndw_ram_off_mask; > + > + /* PKA EIP154 MMIO base address*/ > + mem_res->eip154_base = pka_dev->resource[acpi_mem_idx]->start; > + mem_res->eip154_size = pka_dev->resource[acpi_mem_idx]->end - > + mem_res->eip154_base + 1; > + acpi_mem_idx++; > + > + /* PKA window ram base address*/ > + mem_res->wndw_ram_base = pka_dev->resource[acpi_mem_idx]->start; > + mem_res->wndw_ram_size = pka_dev->resource[acpi_mem_idx]->end - > + mem_res->wndw_ram_base + 1; > + acpi_mem_idx++; > + > + /* PKA alternate window ram base address > + * Note: Here the size of all the alt window ram is same, depicted by > + * 'alt_wndw_ram_size' variable. All alt window ram resources are read > + * here even though not all of them are used currently. > + */ > + mem_res->alt_wndw_ram_0_base = pka_dev->resource[acpi_mem_idx]->start; > + mem_res->alt_wndw_ram_size = pka_dev->resource[acpi_mem_idx]->end - > + mem_res->alt_wndw_ram_0_base + 1; > + > + if (mem_res->alt_wndw_ram_size != PKA_WINDOW_RAM_REGION_SIZE) > + PKA_ERROR(PKA_DRIVER, > + "Alternate Window RAM size read from ACPI is incorrect.\n"); > + > + acpi_mem_idx++; > + > + mem_res->alt_wndw_ram_1_base = pka_dev->resource[acpi_mem_idx]->start; > + acpi_mem_idx++; > + > + mem_res->alt_wndw_ram_2_base = pka_dev->resource[acpi_mem_idx]->start; > + acpi_mem_idx++; > + > + mem_res->alt_wndw_ram_3_base = pka_dev->resource[acpi_mem_idx]->start; > + acpi_mem_idx++; > + > + /* PKA CSR base address*/ > + mem_res->csr_base = pka_dev->resource[acpi_mem_idx]->start; > + mem_res->csr_size = pka_dev->resource[acpi_mem_idx]->end - > + mem_res->csr_base + 1; > +} > + > /* > * Note that this function must be serialized because it calls > * 'pka_dev_register_shim' which manipulates common counters for > * pka devices. > */ > -static int pka_drv_register_device(struct pka_device *pka_dev) > +static int pka_drv_register_device(struct pka_device *pka_dev, > + uint64_t wndw_ram_off_mask) > { > uint32_t pka_shim_id; > - uint64_t pka_shim_base; > - uint64_t pka_shim_size; > uint8_t pka_shim_fw_id; > + struct pka_dev_mem_res mem_res; > > /* Register Shim */ > pka_shim_id = pka_dev->device_id; > - pka_shim_base = pka_dev->resource->start; > - pka_shim_size = pka_dev->resource->end - pka_shim_base; > pka_shim_fw_id = pka_dev->fw_id; > > - pka_dev->shim = pka_dev_register_shim(pka_shim_id, pka_shim_base, > - pka_shim_size, pka_shim_fw_id); > + pka_drv_get_mem_res(pka_dev, &mem_res, wndw_ram_off_mask); > + > + pka_dev->shim = pka_dev_register_shim(pka_shim_id, pka_shim_fw_id, > + &mem_res); > if (!pka_dev->shim) { > PKA_DEBUG(PKA_DRIVER, > - "failed to register shim id=%u, base=0x%llx, size=0x%llx\n", > - pka_shim_id, pka_shim_base, pka_shim_size); > + "failed to register shim id=%u\n", pka_shim_id); > return -EFAULT; > } > > @@ -830,9 +918,11 @@ static int pka_drv_probe_device(struct pka_info *info) > struct device_node *of_node = dev->of_node; > struct platform_device *pdev = to_platform_device(dev); > struct hwrng *trng; > - > - u8 revision; > + const struct acpi_device_id *aid; > + struct pka_drv_plat_info *plat_info; > + uint64_t wndw_ram_off_mask; > int ret; > + enum pka_mem_res_idx acpi_mem_idx; > > if (!info) > return -EINVAL; > @@ -858,8 +948,25 @@ static int pka_drv_probe_device(struct pka_info *info) > info->flag = PKA_DRIVER_FLAG_DEVICE; > mutex_init(&pka_dev->mutex); > > - pka_dev->resource = > - platform_get_resource(pdev, IORESOURCE_MEM, 0); > + for (acpi_mem_idx = PKA_ACPI_EIP154_IDX; > + acpi_mem_idx < PKA_DEVICE_RES_CNT; acpi_mem_idx++) { > + pka_dev->resource[acpi_mem_idx] = > + platform_get_resource(pdev, IORESOURCE_MEM, acpi_mem_idx); > + } > + > + /* Window ram offset mask is platform dependent */ > + aid = acpi_match_device(pka_drv_acpi_ids, dev); > + if (!aid) > + return -ENODEV; > + > + plat_info = (struct pka_drv_plat_info *)aid->driver_data; > + if (plat_info->type <= PKA_PLAT_TYPE_BF2) { > + wndw_ram_off_mask = PKA_WINDOW_RAM_OFFSET_MASK1; > + } else { > + PKA_ERROR(PKA_DRIVER, "Invalid platform type: %d\n", > + (int)plat_info->type); > + return -EINVAL; > + } > > /* Set interrupts */ > ret = platform_get_irq(pdev, 0); > @@ -881,33 +988,11 @@ static int pka_drv_probe_device(struct pka_info *info) > return ret; > } > > - /* > - * Retrieve the firmware identifier based on the device revision. > - * Note that old platform firmware of BF1 does not support the > - * "revision" property, thus set it by default. > - */ > - ret = device_property_read_u8(dev, "rev", &revision); > - if (ret < 0) > - revision = PKA_REVISION_1; > - > - switch (revision) { > - case PKA_REVISION_1: > - pka_dev->fw_id = PKA_FIRMWARE_IMAGE_0_ID; > - break; > - > - case PKA_REVISION_2: > - pka_dev->fw_id = PKA_FIRMWARE_IMAGE_1_ID; > - break; > - > - default: > - PKA_ERROR(PKA_DRIVER, > - "device %u revision %u is not supported\n", > - pka_dev->device_id, revision); > - return -EINVAL; > - } > + /* Firmware version */ > + pka_dev->fw_id = plat_info->fw_id; > > mutex_lock(&pka_drv_lock); > - ret = pka_drv_register_device(pka_dev); > + ret = pka_drv_register_device(pka_dev, wndw_ram_off_mask); > if (ret) { > PKA_DEBUG(PKA_DRIVER, "failed to register shim id=%u\n", > pka_dev->device_id); > @@ -1119,7 +1204,8 @@ static int pka_drv_acpi_probe(struct platform_device *pdev, > if (WARN_ON(!info->acpihid)) > return -EINVAL; > > - if (!strcmp(info->acpihid, pka_ring_acpihid)) { > + if (!strcmp(info->acpihid, pka_ring_acpihid_bf1) > + || !strcmp(info->acpihid, pka_ring_acpihid_bf2)) { > error = pka_drv_probe_ring_device(info); > if (error) { > PKA_DEBUG(PKA_DRIVER, > @@ -1130,7 +1216,8 @@ static int pka_drv_acpi_probe(struct platform_device *pdev, > PKA_DEBUG(PKA_DRIVER, "ring device %s probed\n", > pdev->name); > > - } else if (!strcmp(info->acpihid, pka_acpihid)) { > + } else if (!strcmp(info->acpihid, pka_acpihid_bf1) > + || !strcmp(info->acpihid, pka_acpihid_bf2)) { > error = pka_drv_probe_device(info); > if (error) { > PKA_DEBUG(PKA_DRIVER, > @@ -1262,12 +1349,6 @@ static const struct of_device_id pka_drv_match[] = { > > MODULE_DEVICE_TABLE(of, pka_drv_match); > > -static const struct acpi_device_id pka_drv_acpi_ids[] = { > - { PKA_DEVICE_ACPIHID, 0 }, > - { PKA_RING_DEVICE_ACPIHID, 0 }, > - {}, > -}; > - > MODULE_DEVICE_TABLE(acpi, pka_drv_acpi_ids); > > static struct platform_driver pka_drv = { >
diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h index becb45e..07cbcda 100644 --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_addrs.h @@ -66,75 +66,74 @@ // EIP154 CSRS: -#define PKA_EIP154_ADDR 0x400000 // Global Control Space CSR addresses/offsets. These are accessed from the // ARM as 8 byte reads/writes however only the bottom 32 bits are implemented. -#define PKA_CLOCK_SWITCH_ADDR (0x11C68 | PKA_EIP154_ADDR) -#define PKA_CLK_FORCE_ADDR (0x11C80 | PKA_EIP154_ADDR) -#define MODE_SELECTION_ADDR (0x11C88 | PKA_EIP154_ADDR) -#define PKA_PROT_STATUS_ADDR (0x11C90 | PKA_EIP154_ADDR) -#define PKA_OPTIONS_ADDR (0x11DF0 | PKA_EIP154_ADDR) -#define PKA_VERSION_ADDR (0x11DF8 | PKA_EIP154_ADDR) +#define PKA_CLOCK_SWITCH_ADDR 0x11C68 +#define PKA_CLK_FORCE_ADDR 0x11C80 +#define MODE_SELECTION_ADDR 0x11C88 +#define PKA_PROT_STATUS_ADDR 0x11C90 +#define PKA_OPTIONS_ADDR 0x11DF0 +#define PKA_VERSION_ADDR 0x11DF8 // Advanced Interrupt Controller CSR addresses/offsets. These are accessed // from the ARM as 8 byte reads/writes however only the bottom 32 bits are // implemented. -#define AIC_POL_CTRL_ADDR (0x11E00 | PKA_EIP154_ADDR) -#define AIC_TYPE_CTRL_ADDR (0x11E08 | PKA_EIP154_ADDR) -#define AIC_ENABLE_CTRL_ADDR (0x11E10 | PKA_EIP154_ADDR) -#define AIC_RAW_STAT_ADDR (0x11E18 | PKA_EIP154_ADDR) -#define AIC_ENABLE_SET_ADDR (0x11E18 | PKA_EIP154_ADDR) -#define AIC_ENABLED_STAT_ADDR (0x11E20 | PKA_EIP154_ADDR) -#define AIC_ACK_ADDR (0x11E20 | PKA_EIP154_ADDR) -#define AIC_ENABLE_CLR_ADDR (0x11E28 | PKA_EIP154_ADDR) -#define AIC_OPTIONS_ADDR (0x11E30 | PKA_EIP154_ADDR) -#define AIC_VERSION_ADDR (0x11E38 | PKA_EIP154_ADDR) +#define AIC_POL_CTRL_ADDR 0x11E00 +#define AIC_TYPE_CTRL_ADDR 0x11E08 +#define AIC_ENABLE_CTRL_ADDR 0x11E10 +#define AIC_RAW_STAT_ADDR 0x11E18 +#define AIC_ENABLE_SET_ADDR 0x11E18 +#define AIC_ENABLED_STAT_ADDR 0x11E20 +#define AIC_ACK_ADDR 0x11E20 +#define AIC_ENABLE_CLR_ADDR 0x11E28 +#define AIC_OPTIONS_ADDR 0x11E30 +#define AIC_VERSION_ADDR 0x11E38 // The True Random Number Generator CSR addresses/offsets. These are accessed // from the ARM as 8 byte reads/writes however only the bottom 32 bits are // implemented. -#define TRNG_OUTPUT_0_ADDR (0x12000 | PKA_EIP154_ADDR) -#define TRNG_OUTPUT_1_ADDR (0x12008 | PKA_EIP154_ADDR) -#define TRNG_OUTPUT_2_ADDR (0x12010 | PKA_EIP154_ADDR) -#define TRNG_OUTPUT_3_ADDR (0x12018 | PKA_EIP154_ADDR) -#define TRNG_STATUS_ADDR (0x12020 | PKA_EIP154_ADDR) -#define TRNG_INTACK_ADDR (0x12020 | PKA_EIP154_ADDR) -#define TRNG_CONTROL_ADDR (0x12028 | PKA_EIP154_ADDR) -#define TRNG_CONFIG_ADDR (0x12030 | PKA_EIP154_ADDR) -#define TRNG_ALARMCNT_ADDR (0x12038 | PKA_EIP154_ADDR) -#define TRNG_FROENABLE_ADDR (0x12040 | PKA_EIP154_ADDR) -#define TRNG_FRODETUNE_ADDR (0x12048 | PKA_EIP154_ADDR) -#define TRNG_ALARMMASK_ADDR (0x12050 | PKA_EIP154_ADDR) -#define TRNG_ALARMSTOP_ADDR (0x12058 | PKA_EIP154_ADDR) -#define TRNG_BLOCKCNT_ADDR (0x120E8 | PKA_EIP154_ADDR) -#define TRNG_OPTIONS_ADDR (0x120F0 | PKA_EIP154_ADDR) +#define TRNG_OUTPUT_0_ADDR 0x12000 +#define TRNG_OUTPUT_1_ADDR 0x12008 +#define TRNG_OUTPUT_2_ADDR 0x12010 +#define TRNG_OUTPUT_3_ADDR 0x12018 +#define TRNG_STATUS_ADDR 0x12020 +#define TRNG_INTACK_ADDR 0x12020 +#define TRNG_CONTROL_ADDR 0x12028 +#define TRNG_CONFIG_ADDR 0x12030 +#define TRNG_ALARMCNT_ADDR 0x12038 +#define TRNG_FROENABLE_ADDR 0x12040 +#define TRNG_FRODETUNE_ADDR 0x12048 +#define TRNG_ALARMMASK_ADDR 0x12050 +#define TRNG_ALARMSTOP_ADDR 0x12058 +#define TRNG_BLOCKCNT_ADDR 0x120E8 +#define TRNG_OPTIONS_ADDR 0x120F0 // Control register address/offset. This is accessed from the ARM using 8 // byte reads/writes however only the bottom 32 bits are implemented. -#define PKA_MASTER_SEQ_CTRL_ADDR (0x27F90 | PKA_EIP154_ADDR) +#define PKA_MASTER_SEQ_CTRL_ADDR 0x27F90 // Ring CSRs: These are all accessed from the ARM using 8 byte reads/writes // however only the bottom 32 bits are implemented. // Ring 0 CSRS -#define COMMAND_COUNT_0_ADDR (0x80080 | PKA_EIP154_ADDR) -#define RESULT_COUNT_0_ADDR (0x80088 | PKA_EIP154_ADDR) -#define IRQ_THRESH_0_ADDR (0x80090 | PKA_EIP154_ADDR) +#define COMMAND_COUNT_0_ADDR 0x80080 +#define RESULT_COUNT_0_ADDR 0x80088 +#define IRQ_THRESH_0_ADDR 0x80090 // Ring 1 CSRS: -#define COMMAND_COUNT_1_ADDR (0x90080 | PKA_EIP154_ADDR) -#define RESULT_COUNT_1_ADDR (0x90088 | PKA_EIP154_ADDR) -#define IRQ_THRESH_1_ADDR (0x90090 | PKA_EIP154_ADDR) +#define COMMAND_COUNT_1_ADDR 0x90080 +#define RESULT_COUNT_1_ADDR 0x90088 +#define IRQ_THRESH_1_ADDR 0x90090 // Ring 2 CSRS: -#define COMMAND_COUNT_2_ADDR (0xA0080 | PKA_EIP154_ADDR) -#define RESULT_COUNT_2_ADDR (0xA0088 | PKA_EIP154_ADDR) -#define IRQ_THRESH_2_ADDR (0xA0090 | PKA_EIP154_ADDR) +#define COMMAND_COUNT_2_ADDR 0xA0080 +#define RESULT_COUNT_2_ADDR 0xA0088 +#define IRQ_THRESH_2_ADDR 0xA0090 // Ring 3 CSRS: -#define COMMAND_COUNT_3_ADDR (0xB0080 | PKA_EIP154_ADDR) -#define RESULT_COUNT_3_ADDR (0xB0088 | PKA_EIP154_ADDR) -#define IRQ_THRESH_3_ADDR (0xB0090 | PKA_EIP154_ADDR) +#define COMMAND_COUNT_3_ADDR 0xB0080 +#define RESULT_COUNT_3_ADDR 0xB0088 +#define IRQ_THRESH_3_ADDR 0xB0090 // EIP154 RAM regions: Note that the FARM_PROG_RAM_X address range overlaps // with the FARM_DATA_RAM_X and FARM_DATA_RAM_X_EXT address ranges. This @@ -164,115 +163,100 @@ // PKA Farm Data RAM extension size : 4KB --> 8KB // PKA Farm Program RAM size : 8KB --> 16KB // -#define PKA_BUFFER_RAM_BASE (0x00000 | PKA_EIP154_ADDR) +#define PKA_BUFFER_RAM_BASE 0x00000 #define PKA_BUFFER_RAM_SIZE MEM_SIZE_16KB // 0x00000...0x03FFF -#define PKA_SECURE_RAM_BASE (0x20000 | PKA_EIP154_ADDR) +#define PKA_SECURE_RAM_BASE 0x20000 #define PKA_SECURE_RAM_SIZE MEM_SIZE_16KB // 0x20000...0x23FFF -#define PKA_MASTER_PROG_RAM_BASE (0x30000 | PKA_EIP154_ADDR) +#define PKA_MASTER_PROG_RAM_BASE 0x30000 #define PKA_MASTER_PROG_RAM_SIZE MEM_SIZE_64KB // 0x30000...0x3FFFF -#define FARM_DATA_RAM_0_BASE (0x40000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_0_BASE 0x40000 #define FARM_DATA_RAM_0_SIZE MEM_SIZE_8KB // 0x40000...0x41FFF -#define FARM_DATA_RAM_0_EXT_BASE (0x42000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_0_EXT_BASE 0x42000 #define FARM_DATA_RAM_0_EXT_SIZE MEM_SIZE_8KB // 0x42000...0x43FFF -#define FARM_PROG_RAM_0_BASE (0x40000 | PKA_EIP154_ADDR) +#define FARM_PROG_RAM_0_BASE 0x40000 #define FARM_PROG_RAM_0_SIZE MEM_SIZE_16KB // 0x40000...0x43FFF -#define FARM_DATA_RAM_1_BASE (0x44000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_1_BASE 0x44000 #define FARM_DATA_RAM_1_SIZE MEM_SIZE_8KB // 0x44000...0x45FFF -#define FARM_DATA_RAM_1_EXT_BASE (0x46000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_1_EXT_BASE 0x46000 #define FARM_DATA_RAM_1_EXT_SIZE MEM_SIZE_8KB // 0x46000...0x47FFF -#define FARM_PROG_RAM_1_BASE (0x44000 | PKA_EIP154_ADDR) +#define FARM_PROG_RAM_1_BASE 0x44000 #define FARM_PROG_RAM_1_SIZE MEM_SIZE_16KB // 0x44000...0x47FFF -#define FARM_DATA_RAM_2_BASE (0x48000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_2_BASE 0x48000 #define FARM_DATA_RAM_2_SIZE MEM_SIZE_8KB // 0x48000...0x49FFF -#define FARM_DATA_RAM_2_EXT_BASE (0x4A000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_2_EXT_BASE 0x4A000 #define FARM_DATA_RAM_2_EXT_SIZE MEM_SIZE_8KB // 0x4A000...0x4BFFF -#define FARM_PROG_RAM_2_BASE (0x48000 | PKA_EIP154_ADDR) +#define FARM_PROG_RAM_2_BASE 0x48000 #define FARM_PROG_RAM_2_SIZE MEM_SIZE_16KB // 0x48000...0x4BFFF -#define FARM_DATA_RAM_3_BASE (0x4C000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_3_BASE 0x4C000 #define FARM_DATA_RAM_3_SIZE MEM_SIZE_8KB // 0x4C000...0x4DFFF -#define FARM_DATA_RAM_3_EXT_BASE (0x4E000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_3_EXT_BASE 0x4E000 #define FARM_DATA_RAM_3_EXT_SIZE MEM_SIZE_8KB // 0x4E000...0x4FFFF -#define FARM_PROG_RAM_3_BASE (0x4C000 | PKA_EIP154_ADDR) +#define FARM_PROG_RAM_3_BASE 0x4C000 #define FARM_PROG_RAM_3_SIZE MEM_SIZE_16KB // 0x4C000...0x4FFFF -#define FARM_DATA_RAM_4_BASE (0x50000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_4_BASE 0x50000 #define FARM_DATA_RAM_4_SIZE MEM_SIZE_8KB // 0x50000...0x51FFF -#define FARM_DATA_RAM_4_EXT_BASE (0x52000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_4_EXT_BASE 0x52000 #define FARM_DATA_RAM_4_EXT_SIZE MEM_SIZE_8KB // 0x52000...0x53FFF -#define FARM_PROG_RAM_4_BASE (0x50000 | PKA_EIP154_ADDR) +#define FARM_PROG_RAM_4_BASE 0x50000 #define FARM_PROG_RAM_4_SIZE MEM_SIZE_16KB // 0x50000...0x53FFF -#define FARM_DATA_RAM_5_BASE (0x54000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_5_BASE 0x54000 #define FARM_DATA_RAM_5_SIZE MEM_SIZE_8KB // 0x54000...0x55FFF -#define FARM_DATA_RAM_5_EXT_BASE (0x56000 | PKA_EIP154_ADDR) +#define FARM_DATA_RAM_5_EXT_BASE 0x56000 #define FARM_DATA_RAM_5_EXT_SIZE MEM_SIZE_8KB // 0x56000...0x57FFF -#define FARM_PROG_RAM_5_BASE (0x54000 | PKA_EIP154_ADDR) +#define FARM_PROG_RAM_5_BASE 0x54000 #define FARM_PROG_RAM_5_SIZE MEM_SIZE_16KB // 0x54000...0x57FFF // PKA Buffer RAM offsets. These are NOT real CSR's but instead are // specific offset/addresses within the EIP154 PKA_BUFFER_RAM. // Ring 0: -#define RING_CMMD_BASE_0_ADDR (0x00000 | PKA_EIP154_ADDR) -#define RING_RSLT_BASE_0_ADDR (0x00010 | PKA_EIP154_ADDR) -#define RING_SIZE_TYPE_0_ADDR (0x00020 | PKA_EIP154_ADDR) -#define RING_RW_PTRS_0_ADDR (0x00028 | PKA_EIP154_ADDR) -#define RING_RW_STAT_0_ADDR (0x00030 | PKA_EIP154_ADDR) +#define RING_CMMD_BASE_0_ADDR 0x00000 +#define RING_RSLT_BASE_0_ADDR 0x00010 +#define RING_SIZE_TYPE_0_ADDR 0x00020 +#define RING_RW_PTRS_0_ADDR 0x00028 +#define RING_RW_STAT_0_ADDR 0x00030 // Ring 1 -#define RING_CMMD_BASE_1_ADDR (0x00040 | PKA_EIP154_ADDR) -#define RING_RSLT_BASE_1_ADDR (0x00050 | PKA_EIP154_ADDR) -#define RING_SIZE_TYPE_1_ADDR (0x00060 | PKA_EIP154_ADDR) -#define RING_RW_PTRS_1_ADDR (0x00068 | PKA_EIP154_ADDR) -#define RING_RW_STAT_1_ADDR (0x00070 | PKA_EIP154_ADDR) +#define RING_CMMD_BASE_1_ADDR 0x00040 +#define RING_RSLT_BASE_1_ADDR 0x00050 +#define RING_SIZE_TYPE_1_ADDR 0x00060 +#define RING_RW_PTRS_1_ADDR 0x00068 +#define RING_RW_STAT_1_ADDR 0x00070 // Ring 2 -#define RING_CMMD_BASE_2_ADDR (0x00080 | PKA_EIP154_ADDR) -#define RING_RSLT_BASE_2_ADDR (0x00090 | PKA_EIP154_ADDR) -#define RING_SIZE_TYPE_2_ADDR (0x000A0 | PKA_EIP154_ADDR) -#define RING_RW_PTRS_2_ADDR (0x000A8 | PKA_EIP154_ADDR) -#define RING_RW_STAT_2_ADDR (0x000B0 | PKA_EIP154_ADDR) +#define RING_CMMD_BASE_2_ADDR 0x00080 +#define RING_RSLT_BASE_2_ADDR 0x00090 +#define RING_SIZE_TYPE_2_ADDR 0x000A0 +#define RING_RW_PTRS_2_ADDR 0x000A8 +#define RING_RW_STAT_2_ADDR 0x000B0 // Ring 3 -#define RING_CMMD_BASE_3_ADDR (0x000C0 | PKA_EIP154_ADDR) -#define RING_RSLT_BASE_3_ADDR (0x000D0 | PKA_EIP154_ADDR) -#define RING_SIZE_TYPE_3_ADDR (0x000E0 | PKA_EIP154_ADDR) -#define RING_RW_PTRS_3_ADDR (0x000E8 | PKA_EIP154_ADDR) -#define RING_RW_STAT_3_ADDR (0x000F0 | PKA_EIP154_ADDR) +#define RING_CMMD_BASE_3_ADDR 0x000C0 +#define RING_RSLT_BASE_3_ADDR 0x000D0 +#define RING_SIZE_TYPE_3_ADDR 0x000E0 +#define RING_RW_PTRS_3_ADDR 0x000E8 +#define RING_RW_STAT_3_ADDR 0x000F0 // Ring Options -#define PKA_RING_OPTIONS_ADDR (0x07FF8 | PKA_EIP154_ADDR) +#define PKA_RING_OPTIONS_ADDR 0x07FF8 -// Note the registers/memory below include MiCA specific PKA Control/Status -// registers and the 64K RAM's that the EIP-154 calls Host Memory. - -// Note that Window RAM size is 64K however only the low 16K can be accessed. -#define PKA_WINDOW_RAM_BASE 0x500000 -#define PKA_WINDOW_RAM_SIZE MEM_SIZE_64KB +// Alternate Window RAM size #define PKA_WINDOW_RAM_REGION_SIZE MEM_SIZE_16KB -#define PKA_WINDOW_RAM_REGION_0_BASE 0x600000 -#define PKA_WINDOW_RAM_REGION_0_SIZE PKA_WINDOW_RAM_REGION_SIZE -#define PKA_WINDOW_RAM_REGION_1_BASE 0x610000 -#define PKA_WINDOW_RAM_REGION_1_SIZE PKA_WINDOW_RAM_REGION_SIZE -#define PKA_WINDOW_RAM_REGION_2_BASE 0x620000 -#define PKA_WINDOW_RAM_REGION_2_SIZE PKA_WINDOW_RAM_REGION_SIZE -#define PKA_WINDOW_RAM_REGION_3_BASE 0x630000 -#define PKA_WINDOW_RAM_REGION_3_SIZE PKA_WINDOW_RAM_REGION_SIZE - // Currently, we do not use these MiCA specific CSRs. -#define PKI_EXT_CSR_START_ADDR 0x510000 // The PKI (not EIP154) CSR address/offsets: These are all addressed as // 8-byte registers. -#define PKA_INT_MASK_ADDR (0x00 | PKI_EXT_CSR_START_ADDR) -#define PKA_INT_MASK_SET_ADDR (0x08 | PKI_EXT_CSR_START_ADDR) -#define PKA_INT_MASK_RESET_ADDR (0x10 | PKI_EXT_CSR_START_ADDR) -#define PKA_ZEROIZE_ADDR (0x40 | PKI_EXT_CSR_START_ADDR) -#define TST_FRO_ADDR (0x50 | PKI_EXT_CSR_START_ADDR) -#define FRO_COUNT_ADDR (0x58 | PKI_EXT_CSR_START_ADDR) -#define PKA_PARITY_CTL_ADDR (0x60 | PKI_EXT_CSR_START_ADDR) -#define PKA_PARITY_STAT_ADDR (0x68 | PKI_EXT_CSR_START_ADDR) +#define PKA_INT_MASK_ADDR 0x00 +#define PKA_INT_MASK_SET_ADDR 0x08 +#define PKA_INT_MASK_RESET_ADDR 0x10 +#define PKA_ZEROIZE_ADDR 0x40 +#define TST_FRO_ADDR 0x50 +#define FRO_COUNT_ADDR 0x58 +#define PKA_PARITY_CTL_ADDR 0x60 +#define PKA_PARITY_STAT_ADDR 0x68 #endif // __PKA_ADDRS_H__ diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h index 4cda85d..b590477 100644 --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h @@ -53,13 +53,10 @@ // and ring spacing. #define PKA_RING_WORDS_ADDR PKA_BUFFER_RAM_BASE #define PKA_RING_CNTRS_ADDR COMMAND_COUNT_0_ADDR -#define PKA_RING_MEM_0_BASE PKA_WINDOW_RAM_BASE -#define PKA_RING_MEM_1_BASE PKA_WINDOW_RAM_REGION_0_BASE #define PKA_RING_WORDS_SIZE 0x40 // 64 bytes #define PKA_RING_CNTRS_SIZE 0x20 // 32 bytes (3 count registers) -#define PKA_RING_MEM_0_SIZE PKA_WINDOW_RAM_REGION_SIZE -#define PKA_RING_MEM_1_SIZE PKA_WINDOW_RAM_REGION_SIZE +#define PKA_RING_MEM_SIZE 0x4000 // 16K bytes #define PKA_RING_WORDS_SPACING 0x40 // 64 bytes #define PKA_RING_CNTRS_SPACING 0x10000 // 64K bytes @@ -75,11 +72,18 @@ #define PKA_WINDOW_RAM_RING_MEM_SIZE 0x0800 // 2KB #define PKA_WINDOW_RAM_DATA_MEM_SIZE 0x3800 // 14KB +// Offset mask, common to both Window and Alternate Window RAM. +#define PKA_WINDOW_RAM_OFFSET_MASK1 0x730000 + // Macro for mapping PKA Ring address into Window RAM address. It converts the // ring address, either physical address or virtual address, to valid address -// into the Window RAM. This is done assuming the Window RAM base and size. -#define PKA_RING_MEM_ADDR(addr, size) \ - (PKA_WINDOW_RAM_BASE | (((addr) & 0xffff) | \ +// into the Window RAM. This is done assuming the Window RAM base, size and +// mask. Here, base is the actual physical address of the Window RAM, with the +// help of mask it is reduced to Window RAM offset within that PKA block. +// Further, with the help of addr and size, we arrive at the Window RAM +// offset address for a PKA Ring within the given Window RAM. +#define PKA_RING_MEM_ADDR(base, mask, addr, size) \ + ((base & mask) | (((addr) & 0xffff) | \ ((((addr) & ~((size) - 1)) & 0xf0000) >> 2))) // PKA Master Sequencer Control/Status Register diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c index 4539bae..8e4141b 100644 --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.c @@ -175,7 +175,7 @@ static int pka_dev_set_resource_config(pka_dev_shim_t *shim, res_ptr->base = res_base; if (res_type == PKA_DEV_RES_TYPE_MEM) - res_ptr->base = shim->base + res_base; + res_ptr->base = shim->mem_res.eip154_base + res_base; res_ptr->size = res_size; res_ptr->type = res_type; @@ -267,7 +267,6 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, uint32_t ring_cntrs_off; uint32_t ring_mem_off; uint32_t ring_mem_base; - uint32_t ring_mem_size; uint32_t shim_ring_id; uint8_t window_ram_split; @@ -294,7 +293,8 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, // Configure ring information control/status words resource ring_info_words_ptr = &ring->resources.info_words; ring_words_off = shim_ring_id * PKA_RING_WORDS_SPACING; - ring_info_words_ptr->base = ring_words_off + PKA_RING_WORDS_ADDR; + ring_info_words_ptr->base = ring_words_off + shim->mem_res.eip154_base + + PKA_RING_WORDS_ADDR; ring_info_words_ptr->size = PKA_RING_WORDS_SIZE; ring_info_words_ptr->type = PKA_DEV_RES_TYPE_MEM; ring_info_words_ptr->status = PKA_DEV_RES_STATUS_UNMAPPED; @@ -303,7 +303,8 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, // Configure ring counters registers resource ring_counters_ptr = &ring->resources.counters; ring_cntrs_off = shim_ring_id * PKA_RING_CNTRS_SPACING; - ring_counters_ptr->base = ring_cntrs_off + PKA_RING_CNTRS_ADDR; + ring_counters_ptr->base = ring_cntrs_off + shim->mem_res.eip154_base + + PKA_RING_CNTRS_ADDR; ring_counters_ptr->size = PKA_RING_CNTRS_SIZE; ring_counters_ptr->type = PKA_DEV_RES_TYPE_REG; ring_counters_ptr->status = PKA_DEV_RES_STATUS_UNMAPPED; @@ -314,19 +315,17 @@ static int pka_dev_init_ring(pka_dev_ring_t *ring, uint32_t ring_id, if (window_ram_split == PKA_SHIM_WINDOW_RAM_SPLIT_ENABLED) { ring_mem_off = shim_ring_id * PKA_RING_MEM_1_SPACING; - ring_mem_base = ring_mem_off + PKA_RING_MEM_1_BASE; - ring_mem_size = PKA_RING_MEM_1_SIZE; + ring_mem_base = ring_mem_off + shim->mem_res.alt_wndw_ram_0_base; } else { ring_mem_off = shim_ring_id * PKA_RING_MEM_0_SPACING; - ring_mem_base = ring_mem_off + PKA_RING_MEM_0_BASE; - ring_mem_size = PKA_RING_MEM_0_SIZE; + ring_mem_base = ring_mem_off + shim->mem_res.wndw_ram_base; } ring_window_ram_ptr = &ring->resources.window_ram; ring_window_ram_ptr->base = ring_mem_base; - ring_window_ram_ptr->size = ring_mem_size; + ring_window_ram_ptr->size = PKA_RING_MEM_SIZE; ring_window_ram_ptr->type = PKA_DEV_RES_TYPE_MEM; ring_window_ram_ptr->status = PKA_DEV_RES_STATUS_UNMAPPED; ring_window_ram_ptr->name = "PKA_RING_WINDOW"; @@ -474,9 +473,11 @@ static int pka_dev_partition_mem(pka_dev_ring_t *ring) rslt_desc_ring_base = ring_mem_base + cmd_desc_ring_size; cmd_desc_ring_base = - PKA_RING_MEM_ADDR(cmd_desc_ring_base, window_ram_size); + PKA_RING_MEM_ADDR(window_ram_base, shim->mem_res.wndw_ram_off_mask, + cmd_desc_ring_base, window_ram_size); rslt_desc_ring_base = - PKA_RING_MEM_ADDR(rslt_desc_ring_base, window_ram_size); + PKA_RING_MEM_ADDR(window_ram_base, shim->mem_res.wndw_ram_off_mask, + rslt_desc_ring_base, window_ram_size); ring_info = ring->ring_info; // Fill ring information. @@ -629,7 +630,7 @@ static int pka_dev_set_ring_info(pka_dev_ring_t *ring) // Create shim. Set shim parameters and configure shim resources. // It returns 0 on success, a negative error code on failure. static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, - uint64_t shim_base, uint64_t shim_size, uint8_t split) + uint8_t split, struct pka_dev_mem_res *mem_res) { int ret = 0; @@ -652,8 +653,7 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, } shim->shim_id = shim_id; - shim->base = shim_base; - shim->size = shim_size; + shim->mem_res = *mem_res; if (split) shim->window_ram_split = PKA_SHIM_WINDOW_RAM_SPLIT_ENABLED; @@ -674,10 +674,10 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, // Set PKA device Buffer RAM config ret = pka_dev_set_resource_config(shim, &shim->resources.buffer_ram, - PKA_BUFFER_RAM_BASE, - PKA_BUFFER_RAM_SIZE, - PKA_DEV_RES_TYPE_MEM, - "PKA_BUFFER_RAM"); + PKA_BUFFER_RAM_BASE, + PKA_BUFFER_RAM_SIZE, + PKA_DEV_RES_TYPE_MEM, + "PKA_BUFFER_RAM"); if (ret) { PKA_ERROR(PKA_DEV, "unable to set Buffer RAM config\n"); @@ -686,10 +686,10 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, // Set PKA device Master Program RAM config ret = pka_dev_set_resource_config(shim, &shim->resources.master_prog_ram, - PKA_MASTER_PROG_RAM_BASE, - PKA_MASTER_PROG_RAM_SIZE, - PKA_DEV_RES_TYPE_MEM, - "PKA_MASTER_PROG_RAM"); + PKA_MASTER_PROG_RAM_BASE, + PKA_MASTER_PROG_RAM_SIZE, + PKA_DEV_RES_TYPE_MEM, + "PKA_MASTER_PROG_RAM"); if (ret) { PKA_ERROR(PKA_DEV, "unable to set Master Program RAM config\n"); @@ -698,12 +698,12 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, // Set PKA device Master Controller register reg_size = PAGE_SIZE; - reg_base = pka_dev_get_register_base(shim->base, - PKA_MASTER_SEQ_CTRL_ADDR); + reg_base = pka_dev_get_register_base(shim->mem_res.eip154_base, + PKA_MASTER_SEQ_CTRL_ADDR); ret = pka_dev_set_resource_config(shim, &shim->resources.master_seq_ctrl, - reg_base, reg_size, - PKA_DEV_RES_TYPE_REG, - "PKA_MASTER_SEQ_CTRL"); + reg_base, reg_size, + PKA_DEV_RES_TYPE_REG, + "PKA_MASTER_SEQ_CTRL"); if (ret) { PKA_ERROR(PKA_DEV, "unable to set Master Controller register " @@ -713,8 +713,8 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, // Set PKA device AIC registers reg_size = PAGE_SIZE; - reg_base = pka_dev_get_register_base(shim->base, - AIC_POL_CTRL_ADDR); + reg_base = pka_dev_get_register_base(shim->mem_res.eip154_base, + AIC_POL_CTRL_ADDR); ret = pka_dev_set_resource_config(shim, &shim->resources.aic_csr, reg_base, reg_size, PKA_DEV_RES_TYPE_REG, @@ -727,8 +727,8 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, // Set PKA device TRNG registers reg_size = PAGE_SIZE; - reg_base = pka_dev_get_register_base(shim->base, - TRNG_OUTPUT_0_ADDR); + reg_base = pka_dev_get_register_base(shim->mem_res.eip154_base, + TRNG_OUTPUT_0_ADDR); ret = pka_dev_set_resource_config(shim, &shim->resources.trng_csr, reg_base, reg_size, PKA_DEV_RES_TYPE_REG, @@ -741,8 +741,8 @@ static int pka_dev_create_shim(pka_dev_shim_t *shim, uint32_t shim_id, // Set PKA device 'glue' logic registers reg_size = PAGE_SIZE; - reg_base = pka_dev_get_register_base(shim->base, - PKA_INT_MASK_ADDR); + reg_base = pka_dev_get_register_base(shim->mem_res.csr_base, + PKA_INT_MASK_ADDR); ret = pka_dev_set_resource_config(shim, &shim->resources.ext_csr, reg_base, reg_size, PKA_DEV_RES_TYPE_REG, @@ -1433,16 +1433,14 @@ int pka_dev_unregister_ring(pka_dev_ring_t *ring) } static pka_dev_shim_t *__pka_dev_register_shim(uint32_t shim_id, - uint64_t shim_base, - uint64_t shim_size) + struct pka_dev_mem_res *mem_res) { pka_dev_shim_t *shim; uint8_t split; int ret = 0; - PKA_DEBUG(PKA_DEV, "register shim id=%u, start=0x%llx end=0x%llx\n", - shim_id, shim_base, shim_base + shim_size); + PKA_DEBUG(PKA_DEV, "register shim id=%u\n", shim_id); shim = kzalloc(sizeof(pka_dev_shim_t), GFP_KERNEL); if (!shim) @@ -1456,7 +1454,7 @@ static pka_dev_shim_t *__pka_dev_register_shim(uint32_t shim_id, split = PKA_SPLIT_WINDOW_RAM_MODE; // Create PKA shim - ret = pka_dev_create_shim(shim, shim_id, shim_base, shim_size, split); + ret = pka_dev_create_shim(shim, shim_id, split, mem_res); if (ret) { PKA_ERROR(PKA_DEV, "failed to create shim %u\n", shim_id); @@ -1479,14 +1477,14 @@ static pka_dev_shim_t *__pka_dev_register_shim(uint32_t shim_id, return shim; } -pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint64_t shim_base, - uint64_t shim_size, uint8_t shim_fw_id) +pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint8_t shim_fw_id, + struct pka_dev_mem_res *mem_res) { pka_dev_shim_t *shim; pka_firmware_set_id(shim_fw_id); - shim = __pka_dev_register_shim(shim_id, shim_base, shim_size); + shim = __pka_dev_register_shim(shim_id, mem_res); if (shim) { pka_gbl_config.dev_shims[shim->shim_id] = shim; diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h index 5a6cc8fd..b42ab5d 100644 --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_dev.h @@ -159,11 +159,30 @@ typedef struct uint8_t res_cnt; } pka_dev_gbl_shim_res_info_t; +struct pka_dev_mem_res +{ + uint64_t eip154_base; ///< base address for eip154 mmio registers + uint64_t eip154_size; ///< eip154 mmio register region size + + uint64_t wndw_ram_off_mask; ///< common offset mask for alt window ram and window ram + uint64_t wndw_ram_base; ///< base address for window ram + uint64_t wndw_ram_size; ///< window ram region size + + uint64_t alt_wndw_ram_0_base; ///< base address for alternate window ram 0 + uint64_t alt_wndw_ram_1_base; ///< base address for alternate window ram 1 + uint64_t alt_wndw_ram_2_base; ///< base address for alternate window ram 2 + uint64_t alt_wndw_ram_3_base; ///< base address for alternate window ram 3 + uint64_t alt_wndw_ram_size; ///< alternate window ram regions size + + uint64_t csr_base; ///< base address for csr registers + uint64_t csr_size; ///< csr area size +}; + + /// PKA Shim structure struct pka_dev_shim_s { - uint64_t base; ///< shim base address - uint64_t size; ///< shim io memory size + struct pka_dev_mem_res mem_res; uint64_t trng_err_cycle; ///< TRNG error cycle @@ -252,8 +271,8 @@ int pka_dev_unregister_ring(pka_dev_ring_t *ring); /// Register PKA IO block. This function initializes a shim and configures its /// related resources, and returns a pointer to that ring. -pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint64_t shim_base, - uint64_t shim_size, uint8_t shim_fw_id); +pka_dev_shim_t *pka_dev_register_shim(uint32_t shim_id, uint8_t shim_fw_id, + struct pka_dev_mem_res *mem_res); /// Unregister PKA IO block int pka_dev_unregister_shim(pka_dev_shim_t *shim); diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c index f93efb66..2290e72 100644 --- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c +++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c @@ -28,11 +28,30 @@ #define PKA_DEVICE_COMPAT "mlx,mlxbf-pka" #define PKA_RING_DEVICE_COMPAT "mlx,mlxbf-pka-ring" -#define PKA_DEVICE_ACPIHID "MLNXBF10" -#define PKA_RING_DEVICE_ACPIHID "MLNXBF11" +#define PKA_DEVICE_ACPIHID_BF1 "MLNXBF10" +#define PKA_RING_DEVICE_ACPIHID_BF1 "MLNXBF11" + +#define PKA_DEVICE_ACPIHID_BF2 "MLNXBF20" +#define PKA_RING_DEVICE_ACPIHID_BF2 "MLNXBF21" #define PKA_DEVICE_ACCESS_MODE 0666 +#define PKA_DEVICE_RES_CNT 7 +enum pka_mem_res_idx { + PKA_ACPI_EIP154_IDX = 0, + PKA_ACPI_WNDW_RAM_IDX, + PKA_ACPI_ALT_WNDW_RAM_0_IDX, + PKA_ACPI_ALT_WNDW_RAM_1_IDX, + PKA_ACPI_ALT_WNDW_RAM_2_IDX, + PKA_ACPI_ALT_WNDW_RAM_3_IDX, + PKA_ACPI_CSR_IDX +}; + +enum pka_plat_type { + PKA_PLAT_TYPE_BF1 = 0, /* Platform type Bluefield-1 */ + PKA_PLAT_TYPE_BF2 /* Platform type Bluefield-2 */ +}; + static DEFINE_MUTEX(pka_drv_lock); static uint32_t pka_device_cnt; @@ -41,8 +60,35 @@ static uint32_t pka_ring_device_cnt; const char pka_compat[] = PKA_DEVICE_COMPAT; const char pka_ring_compat[] = PKA_RING_DEVICE_COMPAT; -const char pka_acpihid[] = PKA_DEVICE_ACPIHID; -const char pka_ring_acpihid[] = PKA_RING_DEVICE_ACPIHID; +const char pka_acpihid_bf1[] = PKA_DEVICE_ACPIHID_BF1; +const char pka_ring_acpihid_bf1[] = PKA_RING_DEVICE_ACPIHID_BF1; + +const char pka_acpihid_bf2[] = PKA_DEVICE_ACPIHID_BF2; +const char pka_ring_acpihid_bf2[] = PKA_RING_DEVICE_ACPIHID_BF2; + +struct pka_drv_plat_info { + enum pka_plat_type type; + uint8_t fw_id; +}; + +static struct pka_drv_plat_info pka_drv_plat[] = { + [PKA_PLAT_TYPE_BF1] = { + .type = PKA_PLAT_TYPE_BF1, + .fw_id = PKA_FIRMWARE_IMAGE_0_ID + }, + [PKA_PLAT_TYPE_BF2] = { + .type = PKA_PLAT_TYPE_BF2, + .fw_id = PKA_FIRMWARE_IMAGE_1_ID + } +}; + +static const struct acpi_device_id pka_drv_acpi_ids[] = { + { PKA_DEVICE_ACPIHID_BF1, (kernel_ulong_t)&pka_drv_plat[PKA_PLAT_TYPE_BF1] }, + { PKA_RING_DEVICE_ACPIHID_BF1, 0 }, + { PKA_DEVICE_ACPIHID_BF2, (kernel_ulong_t)&pka_drv_plat[PKA_PLAT_TYPE_BF2] }, + { PKA_RING_DEVICE_ACPIHID_BF2, 0 }, + {}, +}; struct pka_info { struct device *dev; /* the device this info belongs to */ @@ -59,11 +105,6 @@ struct pka_info { #define PKA_DRIVER_FLAG_RING_DEVICE 1 #define PKA_DRIVER_FLAG_DEVICE 2 -enum { - PKA_REVISION_1 = 1, - PKA_REVISION_2, -}; - struct pka_platdata { struct platform_device *pdev; struct pka_info *info; @@ -138,7 +179,7 @@ struct pka_device { uint32_t device_id; uint8_t fw_id; /* firmware identifier */ struct mutex mutex; - struct resource *resource; + struct resource *resource[PKA_DEVICE_RES_CNT]; pka_dev_shim_t *shim; long irq; /* interrupt number */ struct hwrng rng; @@ -189,7 +230,6 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) struct pka_ring_region *region; pka_dev_ring_t *ring; pka_dev_res_t *res; - uint64_t shim_base; uint32_t num_regions; ring = ring_dev->ring; @@ -204,15 +244,13 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) if (!ring_dev->regions) return -ENOMEM; - shim_base = ring->shim->base; - /* Information words region */ res = &ring->resources.info_words; region = &ring_dev->regions[PKA_RING_REGION_WORDS_IDX]; /* map offset to the physical address */ region->off = PKA_RING_REGION_INDEX_TO_OFFSET(PKA_RING_REGION_WORDS_IDX); - region->addr = res->base + shim_base; + region->addr = res->base; region->size = res->size; region->type = PKA_RING_RES_TYPE_WORDS; region->flags |= (PKA_RING_REGION_FLAG_MMAP | @@ -225,7 +263,7 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) /* map offset to the physical address */ region->off = PKA_RING_REGION_INDEX_TO_OFFSET(PKA_RING_REGION_CNTRS_IDX); - region->addr = res->base + shim_base; + region->addr = res->base; region->size = res->size; region->type = PKA_RING_RES_TYPE_CNTRS; region->flags |= (PKA_RING_REGION_FLAG_MMAP | @@ -238,7 +276,7 @@ static int pka_drv_ring_regions_init(struct pka_ring_device *ring_dev) /* map offset to the physical address */ region->off = PKA_RING_REGION_INDEX_TO_OFFSET(PKA_RING_REGION_MEM_IDX); - region->addr = res->base + shim_base; + region->addr = res->base; region->size = res->size; region->type = PKA_RING_RES_TYPE_MEM; region->flags |= (PKA_RING_REGION_FLAG_MMAP | @@ -714,30 +752,80 @@ static void pka_drv_destroy_class(void) } #endif +static void pka_drv_get_mem_res(struct pka_device *pka_dev, + struct pka_dev_mem_res *mem_res, + uint64_t wndw_ram_off_mask) +{ + enum pka_mem_res_idx acpi_mem_idx; + + acpi_mem_idx = PKA_ACPI_EIP154_IDX; + mem_res->wndw_ram_off_mask = wndw_ram_off_mask; + + /* PKA EIP154 MMIO base address*/ + mem_res->eip154_base = pka_dev->resource[acpi_mem_idx]->start; + mem_res->eip154_size = pka_dev->resource[acpi_mem_idx]->end - + mem_res->eip154_base + 1; + acpi_mem_idx++; + + /* PKA window ram base address*/ + mem_res->wndw_ram_base = pka_dev->resource[acpi_mem_idx]->start; + mem_res->wndw_ram_size = pka_dev->resource[acpi_mem_idx]->end - + mem_res->wndw_ram_base + 1; + acpi_mem_idx++; + + /* PKA alternate window ram base address + * Note: Here the size of all the alt window ram is same, depicted by + * 'alt_wndw_ram_size' variable. All alt window ram resources are read + * here even though not all of them are used currently. + */ + mem_res->alt_wndw_ram_0_base = pka_dev->resource[acpi_mem_idx]->start; + mem_res->alt_wndw_ram_size = pka_dev->resource[acpi_mem_idx]->end - + mem_res->alt_wndw_ram_0_base + 1; + + if (mem_res->alt_wndw_ram_size != PKA_WINDOW_RAM_REGION_SIZE) + PKA_ERROR(PKA_DRIVER, + "Alternate Window RAM size read from ACPI is incorrect.\n"); + + acpi_mem_idx++; + + mem_res->alt_wndw_ram_1_base = pka_dev->resource[acpi_mem_idx]->start; + acpi_mem_idx++; + + mem_res->alt_wndw_ram_2_base = pka_dev->resource[acpi_mem_idx]->start; + acpi_mem_idx++; + + mem_res->alt_wndw_ram_3_base = pka_dev->resource[acpi_mem_idx]->start; + acpi_mem_idx++; + + /* PKA CSR base address*/ + mem_res->csr_base = pka_dev->resource[acpi_mem_idx]->start; + mem_res->csr_size = pka_dev->resource[acpi_mem_idx]->end - + mem_res->csr_base + 1; +} + /* * Note that this function must be serialized because it calls * 'pka_dev_register_shim' which manipulates common counters for * pka devices. */ -static int pka_drv_register_device(struct pka_device *pka_dev) +static int pka_drv_register_device(struct pka_device *pka_dev, + uint64_t wndw_ram_off_mask) { uint32_t pka_shim_id; - uint64_t pka_shim_base; - uint64_t pka_shim_size; uint8_t pka_shim_fw_id; + struct pka_dev_mem_res mem_res; /* Register Shim */ pka_shim_id = pka_dev->device_id; - pka_shim_base = pka_dev->resource->start; - pka_shim_size = pka_dev->resource->end - pka_shim_base; pka_shim_fw_id = pka_dev->fw_id; - pka_dev->shim = pka_dev_register_shim(pka_shim_id, pka_shim_base, - pka_shim_size, pka_shim_fw_id); + pka_drv_get_mem_res(pka_dev, &mem_res, wndw_ram_off_mask); + + pka_dev->shim = pka_dev_register_shim(pka_shim_id, pka_shim_fw_id, + &mem_res); if (!pka_dev->shim) { PKA_DEBUG(PKA_DRIVER, - "failed to register shim id=%u, base=0x%llx, size=0x%llx\n", - pka_shim_id, pka_shim_base, pka_shim_size); + "failed to register shim id=%u\n", pka_shim_id); return -EFAULT; } @@ -830,9 +918,11 @@ static int pka_drv_probe_device(struct pka_info *info) struct device_node *of_node = dev->of_node; struct platform_device *pdev = to_platform_device(dev); struct hwrng *trng; - - u8 revision; + const struct acpi_device_id *aid; + struct pka_drv_plat_info *plat_info; + uint64_t wndw_ram_off_mask; int ret; + enum pka_mem_res_idx acpi_mem_idx; if (!info) return -EINVAL; @@ -858,8 +948,25 @@ static int pka_drv_probe_device(struct pka_info *info) info->flag = PKA_DRIVER_FLAG_DEVICE; mutex_init(&pka_dev->mutex); - pka_dev->resource = - platform_get_resource(pdev, IORESOURCE_MEM, 0); + for (acpi_mem_idx = PKA_ACPI_EIP154_IDX; + acpi_mem_idx < PKA_DEVICE_RES_CNT; acpi_mem_idx++) { + pka_dev->resource[acpi_mem_idx] = + platform_get_resource(pdev, IORESOURCE_MEM, acpi_mem_idx); + } + + /* Window ram offset mask is platform dependent */ + aid = acpi_match_device(pka_drv_acpi_ids, dev); + if (!aid) + return -ENODEV; + + plat_info = (struct pka_drv_plat_info *)aid->driver_data; + if (plat_info->type <= PKA_PLAT_TYPE_BF2) { + wndw_ram_off_mask = PKA_WINDOW_RAM_OFFSET_MASK1; + } else { + PKA_ERROR(PKA_DRIVER, "Invalid platform type: %d\n", + (int)plat_info->type); + return -EINVAL; + } /* Set interrupts */ ret = platform_get_irq(pdev, 0); @@ -881,33 +988,11 @@ static int pka_drv_probe_device(struct pka_info *info) return ret; } - /* - * Retrieve the firmware identifier based on the device revision. - * Note that old platform firmware of BF1 does not support the - * "revision" property, thus set it by default. - */ - ret = device_property_read_u8(dev, "rev", &revision); - if (ret < 0) - revision = PKA_REVISION_1; - - switch (revision) { - case PKA_REVISION_1: - pka_dev->fw_id = PKA_FIRMWARE_IMAGE_0_ID; - break; - - case PKA_REVISION_2: - pka_dev->fw_id = PKA_FIRMWARE_IMAGE_1_ID; - break; - - default: - PKA_ERROR(PKA_DRIVER, - "device %u revision %u is not supported\n", - pka_dev->device_id, revision); - return -EINVAL; - } + /* Firmware version */ + pka_dev->fw_id = plat_info->fw_id; mutex_lock(&pka_drv_lock); - ret = pka_drv_register_device(pka_dev); + ret = pka_drv_register_device(pka_dev, wndw_ram_off_mask); if (ret) { PKA_DEBUG(PKA_DRIVER, "failed to register shim id=%u\n", pka_dev->device_id); @@ -1119,7 +1204,8 @@ static int pka_drv_acpi_probe(struct platform_device *pdev, if (WARN_ON(!info->acpihid)) return -EINVAL; - if (!strcmp(info->acpihid, pka_ring_acpihid)) { + if (!strcmp(info->acpihid, pka_ring_acpihid_bf1) + || !strcmp(info->acpihid, pka_ring_acpihid_bf2)) { error = pka_drv_probe_ring_device(info); if (error) { PKA_DEBUG(PKA_DRIVER, @@ -1130,7 +1216,8 @@ static int pka_drv_acpi_probe(struct platform_device *pdev, PKA_DEBUG(PKA_DRIVER, "ring device %s probed\n", pdev->name); - } else if (!strcmp(info->acpihid, pka_acpihid)) { + } else if (!strcmp(info->acpihid, pka_acpihid_bf1) + || !strcmp(info->acpihid, pka_acpihid_bf2)) { error = pka_drv_probe_device(info); if (error) { PKA_DEBUG(PKA_DRIVER, @@ -1262,12 +1349,6 @@ static const struct of_device_id pka_drv_match[] = { MODULE_DEVICE_TABLE(of, pka_drv_match); -static const struct acpi_device_id pka_drv_acpi_ids[] = { - { PKA_DEVICE_ACPIHID, 0 }, - { PKA_RING_DEVICE_ACPIHID, 0 }, - {}, -}; - MODULE_DEVICE_TABLE(acpi, pka_drv_acpi_ids); static struct platform_driver pka_drv = {