From patchwork Thu Oct 30 13:15:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Gardner X-Patchwork-Id: 405051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) by ozlabs.org (Postfix) with ESMTP id F049E14007B; Fri, 31 Oct 2014 00:16:05 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.76) (envelope-from ) id 1Xjpa4-0002nL-3l; Thu, 30 Oct 2014 13:16:00 +0000 Received: from mail-pd0-f172.google.com ([209.85.192.172]) by huckleberry.canonical.com with esmtp (Exim 4.76) (envelope-from ) id 1XjpZs-0002kW-LV for kernel-team@lists.ubuntu.com; Thu, 30 Oct 2014 13:15:48 +0000 Received: by mail-pd0-f172.google.com with SMTP id r10so5128422pdi.17 for ; Thu, 30 Oct 2014 06:15:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=MBFV/oons6PtE0SP6aryntsCpv4NXvEp2fSuWQ4x41g=; b=LsLVIpiN5ETK7JqqIdPl3UBDUeQz4r3IQcSHatduc4ZQMC0onYpQZNF1xPixUaHVH5 x6bjyCuoCwLE5Lip61padP1OyEBnc6UkWXvrXMC9quzVjIEPOG59V/+rVSjD4NnBbcFu LgmBQd3VQgW4Y75kdbgqfq4IgtWedVtobkCeYaJy+NXghNb56bHucE7xL2mufYugYZa6 8HdW7jUM2EM5IDlqSn2YAMEwiTWRmnIiKgVvoL3ue9pzG9KFOw/QIGvyyecw5gO3ktl1 9eRQsOD6b0NDD0EqRRb8B6oYKXFTVJJnuK1zPuNXbiNzQbjw3oWY4Tzl9LjcmgrGV/X/ bT9w== X-Gm-Message-State: ALoCoQmUn0bSYi+Fs5euX2I4k+wqpe5kK4i8yW3f9qFGsADe6/XGx5wt2wGsMGS0yLaMQHdKMSz9 X-Received: by 10.70.43.168 with SMTP id x8mr17236324pdl.107.1414674947645; Thu, 30 Oct 2014 06:15:47 -0700 (PDT) Received: from gbyte.rtg.local (host-174-45-39-7.hln-mt.client.bresnan.net. [174.45.39.7]) by mx.google.com with ESMTPSA id te2sm7142410pbc.51.2014.10.30.06.15.46 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Oct 2014 06:15:46 -0700 (PDT) From: tim.gardner@canonical.com To: kernel-team@lists.ubuntu.com Subject: [PATCH Utopic SRU 1/4] cxl: Disable secondary hash in segment table Date: Thu, 30 Oct 2014 07:15:29 -0600 Message-Id: <1414674932-6387-2-git-send-email-tim.gardner@canonical.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1414674932-6387-1-git-send-email-tim.gardner@canonical.com> References: <1414674932-6387-1-git-send-email-tim.gardner@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.14 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: kernel-team-bounces@lists.ubuntu.com From: Ian Munsie BugLink: http://bugs.launchpad.net/bugs/1387523 This patch simplifies the process of finding a free segment table entry by disabling the secondary hash. This reduces the number of possible entries in the segment table for a given address from 16 to 8. Due to the large segment sizes we use it is extremely unlikely that the secondary hash would ever have been used in practice, so this should not have any negative impacts and may even improve performance due to the reduced number of comparisons that software & hardware need to perform. This patch clears the SC bit in the hardware's state register (CXL_PSL_SR_An) to disable the secondary hash in the hardware since we can no longer fill out entries using it. Signed-off-by: Ian Munsie Reviewed-by: Aneesh Kumar K.V Signed-off-by: Michael Ellerman (cherry picked from commit 5100a9d6444bf205de49190431b0d08de43b86e9) Signed-off-by: Tim Gardner --- drivers/misc/cxl/fault.c | 30 ++++++++---------------------- drivers/misc/cxl/native.c | 4 ++-- 2 files changed, 10 insertions(+), 24 deletions(-) diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c index 69506eb..d0e97fd 100644 --- a/drivers/misc/cxl/fault.c +++ b/drivers/misc/cxl/fault.c @@ -22,29 +22,19 @@ #include "cxl.h" static struct cxl_sste* find_free_sste(struct cxl_sste *primary_group, - bool sec_hash, - struct cxl_sste *secondary_group, unsigned int *lru) { - unsigned int i, entry; + unsigned int entry; struct cxl_sste *sste, *group = primary_group; - for (i = 0; i < 2; i++) { - for (entry = 0; entry < 8; entry++) { - sste = group + entry; - if (!(be64_to_cpu(sste->esid_data) & SLB_ESID_V)) - return sste; - } - if (!sec_hash) - break; - group = secondary_group; + for (entry = 0; entry < 8; entry++) { + sste = group + entry; + if (!(be64_to_cpu(sste->esid_data) & SLB_ESID_V)) + return sste; } /* Nothing free, select an entry to cast out */ - if (sec_hash && (*lru & 0x8)) - sste = secondary_group + (*lru & 0x7); - else - sste = primary_group + (*lru & 0x7); - *lru = (*lru + 1) & 0xf; + sste = primary_group + *lru; + *lru = (*lru + 1) & 0x7; return sste; } @@ -53,22 +43,18 @@ static void cxl_load_segment(struct cxl_context *ctx, struct copro_slb *slb) { /* mask is the group index, we search primary and secondary here. */ unsigned int mask = (ctx->sst_size >> 7)-1; /* SSTP0[SegTableSize] */ - bool sec_hash = 1; struct cxl_sste *sste; unsigned int hash; unsigned long flags; - sec_hash = !!(cxl_p1n_read(ctx->afu, CXL_PSL_SR_An) & CXL_PSL_SR_An_SC); - if (slb->vsid & SLB_VSID_B_1T) hash = (slb->esid >> SID_SHIFT_1T) & mask; else /* 256M */ hash = (slb->esid >> SID_SHIFT) & mask; spin_lock_irqsave(&ctx->sste_lock, flags); - sste = find_free_sste(ctx->sstp + (hash << 3), sec_hash, - ctx->sstp + ((~hash & mask) << 3), &ctx->sst_lru); + sste = find_free_sste(ctx->sstp + (hash << 3), &ctx->sst_lru); pr_devel("CXL Populating SST[%li]: %#llx %#llx\n", sste - ctx->sstp, slb->vsid, slb->esid); diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c index 623286a..d47532e 100644 --- a/drivers/misc/cxl/native.c +++ b/drivers/misc/cxl/native.c @@ -417,7 +417,7 @@ static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr) ctx->elem->haurp = 0; /* disable */ ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1)); - sr = CXL_PSL_SR_An_SC; + sr = 0; if (ctx->master) sr |= CXL_PSL_SR_An_MP; if (mfspr(SPRN_LPCR) & LPCR_TC) @@ -508,7 +508,7 @@ static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr) u64 sr; int rc; - sr = CXL_PSL_SR_An_SC; + sr = 0; set_endian(sr); if (ctx->master) sr |= CXL_PSL_SR_An_MP;