| Message ID | 1379932978-7241-1-git-send-email-adam.lee@canonical.com |
|---|---|
| State | New |
| Headers | show |
On Mon, Sep 23, 2013 at 06:42:58PM +0800, Adam Lee wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > BugLink: http://bugs.launchpad.net/bugs/1212376 > > The BIOS uses power of two values for the data/link N value. > > Follow suit to make the Zotac DP to dual-HDMI dongle work. > > v2: Clean up the magic numbers and defines > Change the N clamping to be a bit easier on the eye > Rename intel_reduce_ratio to intel_reduce_m_n_ratio > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49402 > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59810 > Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> > [Haitao Zhang: backport to 3.8 from commit a65851af59387146a28a928c3e7bb17dabc5db72 upstream] > Signed-off-by: Haitao Zhang <haitao.zhang@canonical.com> > Signed-off-by: Kamal Mostafa <kamal@canonical.com> > Signed-off-by: Brad Figg <brad.figg@canonical.com> > (cherry picked from commit b92ae13bf2b9610bef48c1b64c0b4dcdf47a4053 ubuntu-raring) > Cc: Timo Aaltonen <timo.aaltonen@canonical.com> > Signed-off-by: Adam Lee <adam.lee@canonical.com> > --- > ubuntu/i915/i915_reg.h | 12 ++++-------- > ubuntu/i915/intel_display.c | 23 +++++++++++++++-------- > 2 files changed, 19 insertions(+), 16 deletions(-) > > diff --git a/ubuntu/i915/i915_reg.h b/ubuntu/i915/i915_reg.h > index ce70f0a..da24f9c 100644 > --- a/ubuntu/i915/i915_reg.h > +++ b/ubuntu/i915/i915_reg.h > @@ -2603,14 +2603,14 @@ > #define _PIPEB_GMCH_DATA_M 0x71050 > > /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ > -#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) > -#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 > +#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ > +#define TU_SIZE_MASK (0x3f << 25) > > -#define PIPE_GMCH_DATA_M_MASK (0xffffff) > +#define DATA_LINK_M_N_MASK (0xffffff) > +#define DATA_LINK_N_MAX (0x800000) > > #define _PIPEA_GMCH_DATA_N 0x70054 > #define _PIPEB_GMCH_DATA_N 0x71054 > -#define PIPE_GMCH_DATA_N_MASK (0xffffff) > > /* > * Computing Link M and N values for the Display Port link > @@ -2625,11 +2625,9 @@ > > #define _PIPEA_DP_LINK_M 0x70060 > #define _PIPEB_DP_LINK_M 0x71060 > -#define PIPEA_DP_LINK_M_MASK (0xffffff) > > #define _PIPEA_DP_LINK_N 0x70064 > #define _PIPEB_DP_LINK_N 0x71064 > -#define PIPEA_DP_LINK_N_MASK (0xffffff) > > #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) > #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) > @@ -3295,8 +3293,6 @@ > > > #define _PIPEA_DATA_M1 0x60030 > -#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ > -#define TU_SIZE_MASK 0x7e000000 > #define PIPE_DATA_M1_OFFSET 0 > #define _PIPEA_DATA_N1 0x60034 > #define PIPE_DATA_N1_OFFSET 0 > diff --git a/ubuntu/i915/intel_display.c b/ubuntu/i915/intel_display.c > index 31dcfa4..52d639d 100644 > --- a/ubuntu/i915/intel_display.c > +++ b/ubuntu/i915/intel_display.c > @@ -4042,26 +4042,33 @@ struct fdi_m_n { > static void > fdi_reduce_ratio(u32 *num, u32 *den) > { > - while (*num > 0xffffff || *den > 0xffffff) { > + while (*num > DATA_LINK_M_N_MASK || > + *den > DATA_LINK_M_N_MASK) { > *num >>= 1; > *den >>= 1; > } > } > > +static void compute_m_n(unsigned int m, unsigned int n, > + uint32_t *ret_m, uint32_t *ret_n) > +{ > + *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); > + *ret_m = div_u64((uint64_t) m * *ret_n, n); > + fdi_reduce_ratio(ret_m, ret_n); > +} > + > static void > ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, > int link_clock, struct fdi_m_n *m_n) > { > m_n->tu = 64; /* default size */ > > - /* BUG_ON(pixel_clock > INT_MAX / 36); */ > - m_n->gmch_m = bits_per_pixel * pixel_clock; > - m_n->gmch_n = link_clock * nlanes * 8; > - fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); > + compute_m_n(bits_per_pixel * pixel_clock, > + link_clock * nlanes * 8, > + &m_n->gmch_m, &m_n->gmch_n); > > - m_n->link_m = pixel_clock; > - m_n->link_n = link_clock; > - fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); > + compute_m_n(pixel_clock, link_clock, > + &m_n->link_m, &m_n->link_n); > } > > static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) Seems to do what is claimed (as much as just reading code can prove) and looks to match what is applied to R. Acked-by: Andy Whitcroft <apw@canonical.com> -apw
Applied to Quantal. -apw
diff --git a/ubuntu/i915/i915_reg.h b/ubuntu/i915/i915_reg.h index ce70f0a..da24f9c 100644 --- a/ubuntu/i915/i915_reg.h +++ b/ubuntu/i915/i915_reg.h @@ -2603,14 +2603,14 @@ #define _PIPEB_GMCH_DATA_M 0x71050 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ -#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) -#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 +#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ +#define TU_SIZE_MASK (0x3f << 25) -#define PIPE_GMCH_DATA_M_MASK (0xffffff) +#define DATA_LINK_M_N_MASK (0xffffff) +#define DATA_LINK_N_MAX (0x800000) #define _PIPEA_GMCH_DATA_N 0x70054 #define _PIPEB_GMCH_DATA_N 0x71054 -#define PIPE_GMCH_DATA_N_MASK (0xffffff) /* * Computing Link M and N values for the Display Port link @@ -2625,11 +2625,9 @@ #define _PIPEA_DP_LINK_M 0x70060 #define _PIPEB_DP_LINK_M 0x71060 -#define PIPEA_DP_LINK_M_MASK (0xffffff) #define _PIPEA_DP_LINK_N 0x70064 #define _PIPEB_DP_LINK_N 0x71064 -#define PIPEA_DP_LINK_N_MASK (0xffffff) #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) @@ -3295,8 +3293,6 @@ #define _PIPEA_DATA_M1 0x60030 -#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ -#define TU_SIZE_MASK 0x7e000000 #define PIPE_DATA_M1_OFFSET 0 #define _PIPEA_DATA_N1 0x60034 #define PIPE_DATA_N1_OFFSET 0 diff --git a/ubuntu/i915/intel_display.c b/ubuntu/i915/intel_display.c index 31dcfa4..52d639d 100644 --- a/ubuntu/i915/intel_display.c +++ b/ubuntu/i915/intel_display.c @@ -4042,26 +4042,33 @@ struct fdi_m_n { static void fdi_reduce_ratio(u32 *num, u32 *den) { - while (*num > 0xffffff || *den > 0xffffff) { + while (*num > DATA_LINK_M_N_MASK || + *den > DATA_LINK_M_N_MASK) { *num >>= 1; *den >>= 1; } } +static void compute_m_n(unsigned int m, unsigned int n, + uint32_t *ret_m, uint32_t *ret_n) +{ + *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); + *ret_m = div_u64((uint64_t) m * *ret_n, n); + fdi_reduce_ratio(ret_m, ret_n); +} + static void ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, int link_clock, struct fdi_m_n *m_n) { m_n->tu = 64; /* default size */ - /* BUG_ON(pixel_clock > INT_MAX / 36); */ - m_n->gmch_m = bits_per_pixel * pixel_clock; - m_n->gmch_n = link_clock * nlanes * 8; - fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); + compute_m_n(bits_per_pixel * pixel_clock, + link_clock * nlanes * 8, + &m_n->gmch_m, &m_n->gmch_n); - m_n->link_m = pixel_clock; - m_n->link_n = link_clock; - fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); + compute_m_n(pixel_clock, link_clock, + &m_n->link_m, &m_n->link_n); } static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)