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[120.62.191.176]) by mx.google.com with ESMTPSA id ov5sm2309320pdb.91.2015.03.25.05.09.58 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Mar 2015 05:09:59 -0700 (PDT) From: Sanchayan Maity To: u-boot@lists.denx.de, sbabic@denx.de Date: Wed, 25 Mar 2015 17:37:28 +0530 Message-Id: X-Mailer: git-send-email 2.3.3 In-Reply-To: References: In-Reply-To: References: X-Mailman-Approved-At: Wed, 25 Mar 2015 13:32:41 +0100 Cc: marek@denx.de, trini@konsulko.com, Sanchayan Maity , marcel@ziswiler.com Subject: [U-Boot] [PATCH 3/6] ARM: vf610: Add SoC and CPU type detection X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Vybrid product family consists of several rather similar SoC which can be determined by softare during boot time. This allows use of variable ${soc} for Linux device tree files. Detect VF5xx CPU's by reading the CPU count register. We can determine the second number of the CPU type (VF6x0) which indicates the presence of a L2 cache. Signed-off-by: Stefan Agner Signed-off-by: Sanchayan Maity --- arch/arm/cpu/armv7/vf610/generic.c | 29 +++++++++++++++++++++++++++-- arch/arm/include/asm/arch-vf610/imx-regs.h | 12 ++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 92aaad9..3bdc221 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -18,6 +18,8 @@ DECLARE_GLOBAL_DATA_PTR; #endif +static char soc_type[] = "xx0"; + #ifdef CONFIG_MXC_OCOTP void enable_ocotp_clk(unsigned char enable) { @@ -284,14 +286,37 @@ static char *get_reset_cause(void) int print_cpuinfo(void) { - printf("CPU: Freescale Vybrid VF610 at %d MHz\n", - mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("CPU: Freescale Vybrid VF%s at %d MHz\n", + soc_type, mxc_get_clock(MXC_ARM_CLK) / 1000000); printf("Reset cause: %s\n", get_reset_cause()); return 0; } #endif +int arch_cpu_init(void) +{ + struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR; + + soc_type[0] = mscm->cpxcount ? '6' : '5'; /*Dual Core => VF6x0 */ + soc_type[1] = mscm->cpxcfg1 ? '1' : '0'; /* L2 Cache => VFx10 */ + + return 0; +} + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + char soc[6]; + + strcat(soc, "vf"); + strcat(soc, soc_type); + setenv("soc", soc); + + return 0; +} +#endif + int cpu_eth_init(bd_t *bis) { int rc = -ENODEV; diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index aa60031..a5908ca 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -457,6 +457,18 @@ struct scsc_reg { u32 sosc_ctr; }; +/* MSCM */ +struct mscm { + u32 cpxtype; + u32 cpxnum; + u32 cpxmaster; + u32 cpxcount; + u32 cpxcfg0; + u32 cpxcfg1; + u32 cpxcfg2; + u32 cpxcfg3; +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_IMX_REGS_H__ */