From patchwork Thu Nov 12 08:36:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VpamllIEdhbyAo6auY5oOf5p2wKQ==?= X-Patchwork-Id: 1398773 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=BG5XLavW; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CWw7l3frGz9s0b for ; Thu, 12 Nov 2020 19:41:55 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B661F8257D; Thu, 12 Nov 2020 09:38:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="BG5XLavW"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8977A825AC; Thu, 12 Nov 2020 09:37:36 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.8 required=5.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MIME_BASE64_TEXT,RDNS_NONE,SPF_HELO_NONE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw02.mediatek.com (unknown [1.203.163.81]) by phobos.denx.de (Postfix) with ESMTP id 8739F8259C for ; Thu, 12 Nov 2020 09:37:10 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=weijie.gao@mediatek.com X-UUID: 8fc65dca8b684977b1e4b80d9f17087d-20201112 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=vtLbQHWEZlKJl0x17G8ryWIUqqOmBuURky4DiMCvxK8=; b=BG5XLavWJ5286nOlAY99ggokb/rNMeEPpK1HaAYzCP8BmU2k9bVp3t1Ga2KKyiyYkVew4tCP41TLiKzZG+axIwxNXc8B9yeN3zNa3rVanXOuUBBln5hcaJ3908ZLrNlc8xVNE/g8PT4BWw7vfIrp1sgX5t5EiSu9vPnIdduRJwA=; X-UUID: 8fc65dca8b684977b1e4b80d9f17087d-20201112 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 347009599; Thu, 12 Nov 2020 16:37:01 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Nov 2020 16:36:59 +0800 Received: from mcddlt001.mediatek.inc (10.19.240.15) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Nov 2020 16:36:58 +0800 From: Weijie Gao To: CC: GSS_MTK_Uboot_upstream , Daniel Schwierzeck , Stefan Roese , Stefan Roese , Peng Fan , Weijie Gao Subject: [PATCH v4 19/23] mmc: mtk-sd: fix sclk cycles shift value Date: Thu, 12 Nov 2020 16:36:57 +0800 Message-ID: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 X-TM-SNTS-SMTP: 459B94F11ED6974E321123FB92CB9EABAD40A63F43F76AD6C69D68C4C58A31792000:8 X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean It turns out that the sclk cycles used by mt7620/mt7628 is the same as other chips (20 bits, 1048576), not 65536. This patch removes sclk_cycle_shift from dev_comp, and uses a macro with a value 20 instead. Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao --- v4 changes: none v3 changes: new --- drivers/mmc/mtk-sd.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 4f9fa7d0ec..63ff68272c 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -166,6 +166,8 @@ #define DEFAULT_CD_DEBOUNCE 8 +#define SCLK_CYCLES_SHIFT 20 + #define CMD_INTS_MASK \ (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) @@ -256,7 +258,6 @@ struct msdc_top_regs { struct msdc_compatible { u8 clk_div_bits; - u8 sclk_cycle_shift; bool pad_tune0; bool async_fifo; bool data_tune; @@ -722,7 +723,7 @@ static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) { - u32 timeout, clk_ns, shift; + u32 timeout, clk_ns, shift = SCLK_CYCLES_SHIFT; u32 mode = 0; host->timeout_ns = ns; @@ -731,7 +732,6 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) if (host->sclk == 0) { timeout = 0; } else { - shift = host->dev_comp->sclk_cycle_shift; clk_ns = 1000000000UL / host->sclk; timeout = (ns + clk_ns - 1) / clk_ns + clks; /* unit is 1048576 sclk cycles */ @@ -1531,7 +1531,7 @@ static int msdc_drv_probe(struct udevice *dev) host->mmc = &plat->mmc; host->timeout_ns = 100000000; - host->timeout_clks = 3 * (1 << host->dev_comp->sclk_cycle_shift); + host->timeout_clks = 3 * (1 << SCLK_CYCLES_SHIFT); #ifdef CONFIG_PINCTRL pinctrl_select_state(dev, "default"); @@ -1615,7 +1615,6 @@ static const struct dm_mmc_ops msdc_ops = { static const struct msdc_compatible mt7620_compat = { .clk_div_bits = 8, - .sclk_cycle_shift = 16, .pad_tune0 = false, .async_fifo = false, .data_tune = false, @@ -1635,7 +1634,6 @@ static const struct msdc_compatible mt7622_compat = { static const struct msdc_compatible mt7623_compat = { .clk_div_bits = 12, - .sclk_cycle_shift = 20, .pad_tune0 = true, .async_fifo = true, .data_tune = true, @@ -1646,7 +1644,6 @@ static const struct msdc_compatible mt7623_compat = { static const struct msdc_compatible mt8512_compat = { .clk_div_bits = 12, - .sclk_cycle_shift = 20, .pad_tune0 = true, .async_fifo = true, .data_tune = true, @@ -1656,7 +1653,6 @@ static const struct msdc_compatible mt8512_compat = { static const struct msdc_compatible mt8516_compat = { .clk_div_bits = 12, - .sclk_cycle_shift = 20, .pad_tune0 = true, .async_fifo = true, .data_tune = true, @@ -1666,7 +1662,6 @@ static const struct msdc_compatible mt8516_compat = { static const struct msdc_compatible mt8183_compat = { .clk_div_bits = 12, - .sclk_cycle_shift = 20, .pad_tune0 = true, .async_fifo = true, .data_tune = true,