Message ID | eb0fa267bdd3b7a5bfc9af79eb65ff8d508fec72.1445958486.git.michal.simek@xilinx.com |
---|---|
State | Accepted |
Delegated to: | Michal Simek |
Headers | show |
Hi Michal & Edgar, On Tue, Oct 27, 2015 at 10:08 AM, Michal Simek <michal.simek@xilinx.com> wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Zynq has no priority queues. > ZynqMP requires this change to get network working. > This patch was not needed on ep108 for uknown reason even it should be > used. > Tested on Zynq and ZynqMP. > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > drivers/net/zynq_gem.c | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c > index f32862fd0b2e..0e741dd605a6 100644 > --- a/drivers/net/zynq_gem.c > +++ b/drivers/net/zynq_gem.c > @@ -131,6 +131,10 @@ struct zynq_gem_regs { > u32 reserved6[18]; > #define STAT_SIZE 44 > u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ > + u32 reserved7[164]; > + u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ > + u32 reserved8[15]; > + u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ > }; > > /* BD descriptors */ > @@ -304,6 +308,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) > struct phy_device *phydev; > struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; > struct zynq_gem_priv *priv = dev->priv; > + struct emac_bd *dummy_tx_bd = &priv->tx_bd[4]; > + struct emac_bd *dummy_rx_bd = &priv->tx_bd[6]; Please add comments about the magic "4" and "6". > const u32 supported = SUPPORTED_10baseT_Half | > SUPPORTED_10baseT_Full | > SUPPORTED_100baseT_Half | > @@ -352,6 +358,26 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) > /* Setup for Network Control register, MDIO, Rx and Tx enable */ > setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); > > + /* > + * Disable the second priority queue. > + * FIXME: Consider GEMs with more than 2 queues. > + */ Please don't include FIXME comments. > + dummy_tx_bd->addr = 0; > + dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | > + ZYNQ_GEM_TXBUF_LAST_MASK| > + ZYNQ_GEM_TXBUF_USED_MASK; > + > + dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | > + ZYNQ_GEM_RXBUF_NEW_MASK; > + dummy_rx_bd->status = 0; > + flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + > + sizeof(dummy_tx_bd)); > + flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + > + sizeof(dummy_rx_bd)); > + > + writel((u32)dummy_tx_bd, ®s->transmit_q1_ptr); > + writel((u32)dummy_rx_bd, ®s->receive_q1_ptr); > + > priv->init++; > } > > -- > 2.5.0 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index f32862fd0b2e..0e741dd605a6 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -131,6 +131,10 @@ struct zynq_gem_regs { u32 reserved6[18]; #define STAT_SIZE 44 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ + u32 reserved7[164]; + u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ + u32 reserved8[15]; + u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ }; /* BD descriptors */ @@ -304,6 +308,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) struct phy_device *phydev; struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; struct zynq_gem_priv *priv = dev->priv; + struct emac_bd *dummy_tx_bd = &priv->tx_bd[4]; + struct emac_bd *dummy_rx_bd = &priv->tx_bd[6]; const u32 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | @@ -352,6 +358,26 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) /* Setup for Network Control register, MDIO, Rx and Tx enable */ setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); + /* + * Disable the second priority queue. + * FIXME: Consider GEMs with more than 2 queues. + */ + dummy_tx_bd->addr = 0; + dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | + ZYNQ_GEM_TXBUF_LAST_MASK| + ZYNQ_GEM_TXBUF_USED_MASK; + + dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | + ZYNQ_GEM_RXBUF_NEW_MASK; + dummy_rx_bd->status = 0; + flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + + sizeof(dummy_tx_bd)); + flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + + sizeof(dummy_rx_bd)); + + writel((u32)dummy_tx_bd, ®s->transmit_q1_ptr); + writel((u32)dummy_rx_bd, ®s->receive_q1_ptr); + priv->init++; }