diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
index 500dcce4da5c..80f2b83b5899 100644
--- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
+++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c
@@ -220,10 +220,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_WRITE(0XF8000004, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),
diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
index 8be3fb1e35a8..360beaef8ecf 100644
--- a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
@@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0XF8F00200, 1),
diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
index afec4038d3e7..ae4666f7d590 100644
--- a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
@@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
-	EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
index d90a350d3fe0..717955808de6 100644
--- a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
@@ -171,14 +171,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0XF8F00200, 1),
diff --git a/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
index 218307f861c1..82f270c2e18e 100644
--- a/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
@@ -227,10 +227,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0XF8F00200, 1),
@@ -474,10 +470,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0XF8F00200, 1),
@@ -714,10 +706,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0XF8F00200, 1),
diff --git a/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
index 5366956e5bfd..75095ee3d4c7 100644
--- a/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
@@ -219,10 +219,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_WRITE(0xF8000004, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index 39afd82195c2..337af2d9649f 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -7894,70 +7836,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -12094,70 +11972,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
index 88ff7947f20e..248c72861c8e 100644
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -3666,64 +3666,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -8046,70 +7988,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -12359,70 +12237,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
index e9e4e4d077b7..c84ee6b1f214 100644
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -3635,64 +3635,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -7984,70 +7926,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -12266,70 +12144,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
diff --git a/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
index 95cc25a03ed9..b4663818ddb9 100644
--- a/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
@@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
@@ -461,10 +457,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
@@ -699,10 +691,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
diff --git a/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
index 209f5ed7aa2f..254a512ccb6d 100644
--- a/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
@@ -212,10 +212,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@@ -446,10 +442,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@@ -678,10 +670,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
diff --git a/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
index 31c497b3e699..f4362b943b02 100644
--- a/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
@@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@@ -442,10 +438,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
@@ -672,10 +664,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
diff --git a/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
index e966304e4a4d..621de09cc656 100644
--- a/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
@@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
 	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
@@ -467,10 +463,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
 	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
@@ -711,10 +703,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
 	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
diff --git a/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
index 5770c4d5d34c..eefd46d932c8 100644
--- a/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
@@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
@@ -439,10 +435,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
@@ -666,10 +658,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
-	EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKDELAY(0xF8F00200, 1),
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
index df7d3535ddb7..7a15ea572969 100644
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -7860,70 +7802,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
@@ -12026,70 +11904,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
     // .. FINISH: LOCK IT BACK
     // .. START: SRAM/NOR SET OPMODE
     // .. FINISH: SRAM/NOR SET OPMODE
-    // .. START: UART REGISTERS
-    // .. BDIV = 0x6
-    // .. ==> 0XE0001034[7:0] = 0x00000006U
-    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
-    // ..
-    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
-    // .. CD = 0x3e
-    // .. ==> 0XE0001018[15:0] = 0x0000003EU
-    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
-    // ..
-    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
-    // .. STPBRK = 0x0
-    // .. ==> 0XE0001000[8:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
-    // .. STTBRK = 0x0
-    // .. ==> 0XE0001000[7:7] = 0x00000000U
-    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
-    // .. RSTTO = 0x0
-    // .. ==> 0XE0001000[6:6] = 0x00000000U
-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
-    // .. TXDIS = 0x0
-    // .. ==> 0XE0001000[5:5] = 0x00000000U
-    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
-    // .. TXEN = 0x1
-    // .. ==> 0XE0001000[4:4] = 0x00000001U
-    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
-    // .. RXDIS = 0x0
-    // .. ==> 0XE0001000[3:3] = 0x00000000U
-    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
-    // .. RXEN = 0x1
-    // .. ==> 0XE0001000[2:2] = 0x00000001U
-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
-    // .. TXRES = 0x1
-    // .. ==> 0XE0001000[1:1] = 0x00000001U
-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
-    // .. RXRES = 0x1
-    // .. ==> 0XE0001000[0:0] = 0x00000001U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // ..
-    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
-    // .. IRMODE = 0x0
-    // .. ==> 0XE0001004[11:11] = 0x00000000U
-    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
-    // .. UCLKEN = 0x0
-    // .. ==> 0XE0001004[10:10] = 0x00000000U
-    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
-    // .. CHMODE = 0x0
-    // .. ==> 0XE0001004[9:8] = 0x00000000U
-    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
-    // .. NBSTOP = 0x0
-    // .. ==> 0XE0001004[7:6] = 0x00000000U
-    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
-    // .. PAR = 0x4
-    // .. ==> 0XE0001004[5:3] = 0x00000004U
-    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
-    // .. CHRL = 0x0
-    // .. ==> 0XE0001004[2:1] = 0x00000000U
-    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
-    // .. CLKS = 0x0
-    // .. ==> 0XE0001004[0:0] = 0x00000000U
-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
-    // ..
-    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
-    // .. FINISH: UART REGISTERS
     // .. START: QSPI REGISTERS
     // .. Holdb_dr = 1
     // .. ==> 0XE000D000[19:19] = 0x00000001U
diff --git a/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
index d4f0ee796f72..5d573868cb1a 100644
--- a/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
@@ -222,14 +222,6 @@ static unsigned long ps7_peripherals_init_data[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_WRITE(0xF8000004, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
-	EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U),
diff --git a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
index f1b935778047..7c6bc9fa3f42 100644
--- a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
@@ -235,10 +235,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = {
 	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
 	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
 	EMIT_WRITE(0xF8000004, 0x0000767BU),
-	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
-	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
-	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
-	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
 	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
 	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
 	EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00004000U),
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
index c41283704caa..fda6d18dd92c 100644
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -3647,64 +3647,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
 	/* .. FINISH: LOCK IT BACK */
 	/* .. START: SRAM/NOR SET OPMODE */
 	/* .. FINISH: SRAM/NOR SET OPMODE */
-	/* .. START: UART REGISTERS */
-	/* .. BDIV = 0x6 */
-	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
-	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	/* .. CD = 0x7c */
-	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	/* .. STPBRK = 0x0 */
-	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. STTBRK = 0x0 */
-	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. RSTTO = 0x0 */
-	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. TXDIS = 0x0 */
-	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. TXEN = 0x1 */
-	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. RXDIS = 0x0 */
-	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. RXEN = 0x1 */
-	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. TXRES = 0x1 */
-	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. RXRES = 0x1 */
-	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	/* .. CHMODE = 0x0 */
-	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-	/* .. NBSTOP = 0x0 */
-	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. PAR = 0x4 */
-	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-	/* .. CHRL = 0x0 */
-	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. CLKS = 0x0 */
-	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
-	/* .. FINISH: UART REGISTERS */
 	/* .. START: QSPI REGISTERS */
 	/* .. Holdb_dr = 1 */
 	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
@@ -7944,70 +7886,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
 	/* .. FINISH: LOCK IT BACK */
 	/* .. START: SRAM/NOR SET OPMODE */
 	/* .. FINISH: SRAM/NOR SET OPMODE */
-	/* .. START: UART REGISTERS */
-	/* .. BDIV = 0x6 */
-	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
-	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	/* .. CD = 0x7c */
-	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	/* .. STPBRK = 0x0 */
-	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. STTBRK = 0x0 */
-	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. RSTTO = 0x0 */
-	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. TXDIS = 0x0 */
-	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. TXEN = 0x1 */
-	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. RXDIS = 0x0 */
-	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. RXEN = 0x1 */
-	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. TXRES = 0x1 */
-	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. RXRES = 0x1 */
-	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	/* .. IRMODE = 0x0 */
-	/* .. ==> 0XE0001004[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. UCLKEN = 0x0 */
-	/* .. ==> 0XE0001004[10:10] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. CHMODE = 0x0 */
-	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-	/* .. NBSTOP = 0x0 */
-	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. PAR = 0x4 */
-	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-	/* .. CHRL = 0x0 */
-	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. CLKS = 0x0 */
-	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
-	/* .. FINISH: UART REGISTERS */
 	/* .. START: QSPI REGISTERS */
 	/* .. Holdb_dr = 1 */
 	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
@@ -12172,70 +12050,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
 	/* .. FINISH: LOCK IT BACK */
 	/* .. START: SRAM/NOR SET OPMODE */
 	/* .. FINISH: SRAM/NOR SET OPMODE */
-	/* .. START: UART REGISTERS */
-	/* .. BDIV = 0x6 */
-	/* .. ==> 0XE0001034[7:0] = 0x00000006U */
-	/* ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
-	/* .. CD = 0x7c */
-	/* .. ==> 0XE0001018[15:0] = 0x0000007CU */
-	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000007CU */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
-	/* .. STPBRK = 0x0 */
-	/* .. ==> 0XE0001000[8:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
-	/* .. STTBRK = 0x0 */
-	/* .. ==> 0XE0001000[7:7] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
-	/* .. RSTTO = 0x0 */
-	/* .. ==> 0XE0001000[6:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
-	/* .. TXDIS = 0x0 */
-	/* .. ==> 0XE0001000[5:5] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
-	/* .. TXEN = 0x1 */
-	/* .. ==> 0XE0001000[4:4] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
-	/* .. RXDIS = 0x0 */
-	/* .. ==> 0XE0001000[3:3] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
-	/* .. RXEN = 0x1 */
-	/* .. ==> 0XE0001000[2:2] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
-	/* .. TXRES = 0x1 */
-	/* .. ==> 0XE0001000[1:1] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
-	/* .. RXRES = 0x1 */
-	/* .. ==> 0XE0001000[0:0] = 0x00000001U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
-	/* .. IRMODE = 0x0 */
-	/* .. ==> 0XE0001004[11:11] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
-	/* .. UCLKEN = 0x0 */
-	/* .. ==> 0XE0001004[10:10] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
-	/* .. CHMODE = 0x0 */
-	/* .. ==> 0XE0001004[9:8] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000300U    VAL : 0x00000000U */
-	/* .. NBSTOP = 0x0 */
-	/* .. ==> 0XE0001004[7:6] = 0x00000000U */
-	/* ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
-	/* .. PAR = 0x4 */
-	/* .. ==> 0XE0001004[5:3] = 0x00000004U */
-	/* ..     ==> MASK : 0x00000038U    VAL : 0x00000020U */
-	/* .. CHRL = 0x0 */
-	/* .. ==> 0XE0001004[2:1] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
-	/* .. CLKS = 0x0 */
-	/* .. ==> 0XE0001004[0:0] = 0x00000000U */
-	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
-	/* .. */
-	EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
-	/* .. FINISH: UART REGISTERS */
 	/* .. START: QSPI REGISTERS */
 	/* .. Holdb_dr = 1 */
 	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
