diff mbox

[U-Boot,2/2] net: zynq_gem: Add SGMII support for zynqMP

Message ID d006eb8cc95364711baf1db18c38f029d8ebd4fa.1459414390.git.michal.simek@xilinx.com
State Accepted
Commit 845ee5f623861ec274466f85b967d744c5b811e0
Delegated to: Michal Simek
Headers show

Commit Message

Michal Simek March 31, 2016, 8:53 a.m. UTC 
From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

PCS auto negotaiation bit should be enabled
along with SGMII autonegotation enabled
in phy.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 drivers/net/zynq_gem.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

Comments

Joe Hershberger April 25, 2016, 10:20 p.m. UTC | #1 
On Thu, Mar 31, 2016 at 3:53 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
>
> PCS auto negotaiation bit should be enabled
> along with SGMII autonegotation enabled
> in phy.
>
> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
>  drivers/net/zynq_gem.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
> index 52a8f2760012..aec8077f10b3 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -93,6 +93,8 @@ DECLARE_GLOBAL_DATA_PTR;
>
>  #define ZYNQ_GEM_TSR_DONE              0x00000020 /* Tx done mask */
>
> +#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL     0x1000

Use BIT() macro, please.

> +
>  /* Use MII register 1 (MII status register) to detect PHY */
>  #define PHY_DETECT_REG  1
>

Otherwise,

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
diff mbox

Patch

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 52a8f2760012..aec8077f10b3 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -93,6 +93,8 @@  DECLARE_GLOBAL_DATA_PTR;
 
 #define ZYNQ_GEM_TSR_DONE		0x00000020 /* Tx done mask */
 
+#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL	0x1000
+
 /* Use MII register 1 (MII status register) to detect PHY */
 #define PHY_DETECT_REG  1
 
@@ -139,7 +141,9 @@  struct zynq_gem_regs {
 	u32 reserved6[18];
 #define STAT_SIZE	44
 	u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
-	u32 reserved7[164];
+	u32 reserved9[20];
+	u32 pcscntrl;
+	u32 reserved7[143];
 	u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
 	u32 reserved8[15];
 	u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
@@ -432,9 +436,14 @@  static int zynq_gem_init(struct udevice *dev)
 
 	nwconfig = ZYNQ_GEM_NWCFG_INIT;
 
-	if (priv->interface == PHY_INTERFACE_MODE_SGMII)
+	if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
 		nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
 			    ZYNQ_GEM_NWCFG_PCS_SEL;
+#ifdef CONFIG_ARM64
+		writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+		       &regs->pcscntrl);
+#endif
+	}
 
 	switch (priv->phydev->speed) {
 	case SPEED_1000: