From patchwork Mon Oct 14 14:19:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 1176394 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=xilinx.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="E5wGkEw+"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46sLLD6dD8z9sPK for ; Tue, 15 Oct 2019 01:20:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 87E8CC21DF3; Mon, 14 Oct 2019 14:19:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0EBCEC21DF9; Mon, 14 Oct 2019 14:19:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 47182C21C51; Mon, 14 Oct 2019 14:19:38 +0000 (UTC) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by lists.denx.de (Postfix) with ESMTPS id F292AC21BE5 for ; Mon, 14 Oct 2019 14:19:37 +0000 (UTC) Received: by mail-wm1-f66.google.com with SMTP id y135so129408wmc.1 for ; Mon, 14 Oct 2019 07:19:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=kF/9klt6C4LX3Wh+eSHFBKlmhTNDH5en2rcfkFngOEs=; b=E5wGkEw+yFjiT395ROQoEV7HL3Mcn3tj43tRn0fLPy6RXmAyzDq7JSvHES8SESIdKt YNLpVn8ljvEQAibhkVpwZQUiXpG02rUD4+UGBZ37Yha1AwqgNMC27FCigfW20vJrsjLt Q2i1fyUW8xANVr7+U5CmSM86MI9DqjcWEy3rc2wt8TR1shldYg66klQFZc91dMDrCCZa lPyJjICXiYFTs94/4c00QC57moxFO5/JhTeG0aXzBiGTiIimpYuLBjAdVXaV8s0OaKB3 oJAmRr1kzFvaxUPsbej15/UrFOTjKR96F+N75cpItsfjUXLOEWuXqLsJwa24WDaLFW6R eusQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references; bh=kF/9klt6C4LX3Wh+eSHFBKlmhTNDH5en2rcfkFngOEs=; b=iCOJoq2KKvL6lcnmtKJKwBxKLQCFdhHmyUPpf2j4xye62WW6sw+R6MnA01oArkhXAC 9zcl8yYIKgtmzt/MVhBQ2aepx9XaPj02U8it35GWMPAp1WZbITQ9oeeHX2kRxkFM1rf0 oJS7f3pO8xiOE/8caQHF9RhHWEtSyMlSZ7hYjdZUyW2Dcw2tXA+WaH90cbKZrM7D9qdG gzWihcxc6RU6dDH48YsplDnbpS+LIWFMsar6A3zR7PBQLHpgo3vSi+rRZBNhPsiH9NDL V0l04AcRFGI2IzYFGZdP+J+XpjW82XETMXWkVmk6+02jCJFPtznSAGDwZiuBMq7xtc1Z Qqtw== X-Gm-Message-State: APjAAAUyGh22DpzMQ+14rbX717TuamAiSc5/mnkIWGZXR3EFEX3MG0Y+ S2cqPAKsEUwSCbyW6HNQIT5rBYRWzHDZ3CSB X-Google-Smtp-Source: APXvYqx3zdtHnr/YOsPJHZVg37qbbaotram69m+D2NFAoYvLmjV3b0Uwrcx6JCZixvCRKHH0S3jFvw== X-Received: by 2002:a1c:9990:: with SMTP id b138mr15771150wme.176.1571062777323; Mon, 14 Oct 2019 07:19:37 -0700 (PDT) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id b22sm18571468wmj.36.2019.10.14.07.19.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 Oct 2019 07:19:36 -0700 (PDT) From: Michal Simek To: u-boot@lists.denx.de, git@xilinx.com Date: Mon, 14 Oct 2019 16:19:27 +0200 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Cc: Rajan Vaja Subject: [U-Boot] [PATCH 1/7] dt-bindings: clock: zynqmp: Add clk header X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Rajan Vaja Add dt clock header which can be included by dtses. And also use zynqmp-clk compatible string. Signed-off-by: Rajan Vaja Signed-off-by: Michal Simek --- include/dt-bindings/clock/xlnx-zynqmp-clk.h | 126 ++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 include/dt-bindings/clock/xlnx-zynqmp-clk.h diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h new file mode 100644 index 000000000000..cdc4c0b9a374 --- /dev/null +++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Zynq MPSoC Firmware layer + * + * Copyright (C) 2014-2018 Xilinx, Inc. + * + */ + +#ifndef _DT_BINDINGS_CLK_ZYNQMP_H +#define _DT_BINDINGS_CLK_ZYNQMP_H + +#define IOPLL 0 +#define RPLL 1 +#define APLL 2 +#define DPLL 3 +#define VPLL 4 +#define IOPLL_TO_FPD 5 +#define RPLL_TO_FPD 6 +#define APLL_TO_LPD 7 +#define DPLL_TO_LPD 8 +#define VPLL_TO_LPD 9 +#define ACPU 10 +#define ACPU_HALF 11 +#define DBF_FPD 12 +#define DBF_LPD 13 +#define DBG_TRACE 14 +#define DBG_TSTMP 15 +#define DP_VIDEO_REF 16 +#define DP_AUDIO_REF 17 +#define DP_STC_REF 18 +#define GDMA_REF 19 +#define DPDMA_REF 20 +#define DDR_REF 21 +#define SATA_REF 22 +#define PCIE_REF 23 +#define GPU_REF 24 +#define GPU_PP0_REF 25 +#define GPU_PP1_REF 26 +#define TOPSW_MAIN 27 +#define TOPSW_LSBUS 28 +#define GTGREF0_REF 29 +#define LPD_SWITCH 30 +#define LPD_LSBUS 31 +#define USB0_BUS_REF 32 +#define USB1_BUS_REF 33 +#define USB3_DUAL_REF 34 +#define USB0 35 +#define USB1 36 +#define CPU_R5 37 +#define CPU_R5_CORE 38 +#define CSU_SPB 39 +#define CSU_PLL 40 +#define PCAP 41 +#define IOU_SWITCH 42 +#define GEM_TSU_REF 43 +#define GEM_TSU 44 +#define GEM0_TX 45 +#define GEM1_TX 46 +#define GEM2_TX 47 +#define GEM3_TX 48 +#define GEM0_RX 49 +#define GEM1_RX 50 +#define GEM2_RX 51 +#define GEM3_RX 52 +#define QSPI_REF 53 +#define SDIO0_REF 54 +#define SDIO1_REF 55 +#define UART0_REF 56 +#define UART1_REF 57 +#define SPI0_REF 58 +#define SPI1_REF 59 +#define NAND_REF 60 +#define I2C0_REF 61 +#define I2C1_REF 62 +#define CAN0_REF 63 +#define CAN1_REF 64 +#define CAN0 65 +#define CAN1 66 +#define DLL_REF 67 +#define ADMA_REF 68 +#define TIMESTAMP_REF 69 +#define AMS_REF 70 +#define PL0_REF 71 +#define PL1_REF 72 +#define PL2_REF 73 +#define PL3_REF 74 +#define WDT 75 +#define IOPLL_INT 76 +#define IOPLL_PRE_SRC 77 +#define IOPLL_HALF 78 +#define IOPLL_INT_MUX 79 +#define IOPLL_POST_SRC 80 +#define RPLL_INT 81 +#define RPLL_PRE_SRC 82 +#define RPLL_HALF 83 +#define RPLL_INT_MUX 84 +#define RPLL_POST_SRC 85 +#define APLL_INT 86 +#define APLL_PRE_SRC 87 +#define APLL_HALF 88 +#define APLL_INT_MUX 89 +#define APLL_POST_SRC 90 +#define DPLL_INT 91 +#define DPLL_PRE_SRC 92 +#define DPLL_HALF 93 +#define DPLL_INT_MUX 94 +#define DPLL_POST_SRC 95 +#define VPLL_INT 96 +#define VPLL_PRE_SRC 97 +#define VPLL_HALF 98 +#define VPLL_INT_MUX 99 +#define VPLL_POST_SRC 100 +#define CAN0_MIO 101 +#define CAN1_MIO 102 +#define ACPU_FULL 103 +#define GEM0_REF 104 +#define GEM1_REF 105 +#define GEM2_REF 106 +#define GEM3_REF 107 +#define GEM0_REF_UNG 108 +#define GEM1_REF_UNG 109 +#define GEM2_REF_UNG 110 +#define GEM3_REF_UNG 111 +#define LPD_WDT 112 + +#endif