From patchwork Fri Apr 25 13:42:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 342852 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id ED122140168 for ; Fri, 25 Apr 2014 23:45:13 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E0559A7507; Fri, 25 Apr 2014 15:45:05 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IMP4v+RNMvzt; Fri, 25 Apr 2014 15:45:05 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8BF0BA7563; Fri, 25 Apr 2014 15:44:07 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4BD4EA7586 for ; Fri, 25 Apr 2014 15:44:00 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oAU006CebJnL for ; Fri, 25 Apr 2014 15:43:57 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ee0-f42.google.com (mail-ee0-f42.google.com [74.125.83.42]) by theia.denx.de (Postfix) with ESMTPS id 4450CA7569 for ; Fri, 25 Apr 2014 15:43:10 +0200 (CEST) Received: by mail-ee0-f42.google.com with SMTP id d17so2824468eek.15 for ; Fri, 25 Apr 2014 06:43:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references:content-type; bh=G92mIfnG4uRfSQ4PnBiPXQqD5pGJzHUK0I63HBh+QCY=; b=lGePHh5rdprw4FLIrJdtvdd1LaO/XvBUhfq64AmP0NXBFBMmsvhuTGMyeGaEoqPpYW zZkH+TivsKJCG45dkgzu5RGjYMLlwvU9bmM8h58OrQhhZn0NLZmAEj6T2F4aGZ/AlvZ9 A1osTJ4TUG0WGe6DLlJqs0XZ8pA8Eo4DX/rBQNuOEr+DTu84LrghX1WMdmNWEvz1Z8SS DR0hbPtpH91Vt5a12nFC+6Rog5w78Na9e5goAPESbFCRwe9Y8elsLFZubOhusztn8Uly fIGtJ4VMIVNmGIMIuN1pDU3VjptTRXvuAxy88y5VTcK9dOnMAbL6mea7U+fOGm0QAhuQ GEIw== X-Gm-Message-State: ALoCoQk20aDLpkeMOghi0qq1YuU2ELC2KNIP6kC2tImdhGc/lNqG0yQFaUqsnz6RzTi0ytVNoR/S X-Received: by 10.15.45.130 with SMTP id b2mr10906076eew.28.1398433390056; Fri, 25 Apr 2014 06:43:10 -0700 (PDT) Received: from localhost (nat-63.starnet.cz. [178.255.168.63]) by mx.google.com with ESMTPSA id m42sm24969038eex.21.2014.04.25.06.43.08 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Fri, 25 Apr 2014 06:43:09 -0700 (PDT) From: Michal Simek To: u-boot@lists.denx.de Date: Fri, 25 Apr 2014 15:42:19 +0200 Message-Id: X-Mailer: git-send-email 1.8.2.3 In-Reply-To: References: In-Reply-To: References: Cc: git@xilinx.com Subject: [U-Boot] [PATCH 12/18] ARM: zynq: Add MIO detection code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Michal Simek Add run-time MIO pin detection to get actual pin configuration for specific periphery. Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/slcr.c | 50 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-zynq/sys_proto.h | 1 + 2 files changed, 51 insertions(+) -- 1.8.2.3 diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 5ba58fa..51894f9 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -17,6 +17,26 @@ #define SLCR_IDCODE_MASK 0x1F000 #define SLCR_IDCODE_SHIFT 12 +/* + * zynq_slcr_mio_get_status - Get the status of MIO peripheral. + * + * @peri_name: Name of the peripheral for checking MIO status + * @get_pins: Pointer to array of get pin for this peripheral + * @num_pins: Number of pins for this peripheral + * @mask: Mask value + * @check_val: Required check value to get the status of periph + */ +struct zynq_slcr_mio_get_status { + const char *peri_name; + const int *get_pins; + int num_pins; + u32 mask; + u32 check_val; +}; + +static const struct zynq_slcr_mio_get_status mio_periphs[] = { +}; + static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ void zynq_slcr_lock(void) @@ -120,3 +140,33 @@ u32 zynq_slcr_get_idcode(void) return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> SLCR_IDCODE_SHIFT; } + +/* + * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. + * + * @periph: Name of the peripheral + * + * Returns count to indicate the number of pins configured for the + * given @periph. + */ +int zynq_slcr_get_mio_pin_status(const char *periph) +{ + const struct zynq_slcr_mio_get_status *mio_ptr; + int val, i, j; + int mio = 0; + + for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { + if (strcmp(periph, mio_periphs[i].peri_name) == 0) { + mio_ptr = &mio_periphs[i]; + for (j = 0; j < mio_ptr->num_pins; j++) { + val = readl(&slcr_base->mio_pin + [mio_ptr->get_pins[j]]); + if ((val & mio_ptr->mask) == mio_ptr->check_val) + mio++; + } + break; + } + } + + return mio; +} diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 2445a04..53c30ec 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -15,6 +15,7 @@ extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); +extern int zynq_slcr_get_mio_pin_status(const char *periph); extern void zynq_ddrc_init(void); extern unsigned int zynq_get_silicon_version(void);