From patchwork Tue Nov 17 10:17:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hoefle Marco X-Patchwork-Id: 545496 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 00B6614030E for ; Tue, 17 Nov 2015 21:20:19 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 34A944B61D; Tue, 17 Nov 2015 11:20:12 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tIy5KmdzNL5D; Tue, 17 Nov 2015 11:20:12 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0A5314B624; Tue, 17 Nov 2015 11:20:11 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 700D54B62A for ; Tue, 17 Nov 2015 11:18:33 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id t7c8FVjeklKv for ; Tue, 17 Nov 2015 11:18:20 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.nanotronic.ch (mail.nanotronic.ch [217.11.209.63]) by theia.denx.de (Postfix) with ESMTPS id 438764B624 for ; Tue, 17 Nov 2015 11:18:03 +0100 (CET) Received: from LysExc01.nanotronic.local (192.168.101.6) by LysExc01.nanotronic.local (192.168.101.6) with Microsoft SMTP Server (TLS) id 15.0.847.32; Tue, 17 Nov 2015 11:17:24 +0100 Received: from LysExc01.nanotronic.local ([fe80::55cf:cd5b:44f7:b8f9]) by LysExc01.nanotronic.local ([fe80::55cf:cd5b:44f7:b8f9%14]) with mapi id 15.00.0847.030; Tue, 17 Nov 2015 11:17:18 +0100 From: Hoefle Marco To: Michal Simek , Jagan Teki Thread-Topic: AW: AW: AW: [U-Boot] u-boot device model SPI + SPI Flash Thread-Index: AQHRC+e8LNIeHWBPsk+kP5haKudLEp52AZ+AgAAifJD//+JIAIAAKE6ggAKp9gD//+b5gIAFArAAgAF0cfD///hSAAAD62HwAALQcgAAAm+7LgBUoDwAAP3zQHQAN4oTgAA5jbDP///8IICAEpTYZA== Date: Tue, 17 Nov 2015 10:17:17 +0000 Message-ID: References: <7ccbb9ae7fdb4663832167baa173d6b8@LysExc01.nanotronic.local> <0af28a07c7704451be0aa3fce01764d0@LysExc01.nanotronic.local> <320637582ef942f0b71a55d692d254e5@LysExc01.nanotronic.local> <7a85439a92f64a71a5f2b08b3fdc4576@LysExc01.nanotronic.local> <562E2FEE.60605@xilinx.com> <562F61EA.5080303@xilinx.com> <562F8F1A.4050903@xilinx.com> <5631D75E.2000402@xilinx.com> <4a9b0987ae1047fdb9bd0e84160400ac@LysExc01.nanotronic.local> <5639F451.1090501@xilinx.com> <7d9fad7ec38548d4854dc5094a7e0c42@LysExc01.nanotronic.local>, <563B734D.2010902@xilinx.com> In-Reply-To: <563B734D.2010902@xilinx.com> Accept-Language: de-DE, de-CH, en-US Content-Language: de-DE X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [46.140.106.142] MIME-Version: 1.0 Cc: "u-boot@lists.denx.de" , emanuel stiebler Subject: Re: [U-Boot] u-boot device model SPI + SPI Flash X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Hello Michal, hello Jagan, for me the Microblaze SPI port in mainline u-boot does not work with DM. I used Michal's files and modified the addresses and changed Full Ethernet to Ethernet lite and uart to uartlite to match the hardware here. This was not a big step as both Hardware configurations are very similar. The changes between v2016.01-rc1 and the changed/added files are attached as patch. Still the same error: U-Boot 2016.01--95f642905f8dd7c07ac9f5ed49fe14291ab1fb15---00002-g95f6429-dirty (Nov 17 2015 - 10:57:55 +0100) DRAM: 256 MiB Invalid bus 0 (err=-19) *** Warning - spi_flash_probe() failed, using default environment In Michal's files the dts file is split into several files. Here is the resulting tree directly from the u-boot console: => fdt addr 0x8044fda0 => fdt print / { #address-cells = <0x00000001>; #size-cells = <0x00000001>; compatible = "xlnx,microblaze"; model = "Xilinx-AC701-AXI-full-2015.4"; cpus { #address-cells = <0x00000001>; #cpus = <0x00000001>; #size-cells = <0x00000000>; cpu@0 { bus-handle = <0x00000001>; clock-frequency = <0x05f5e100>; clocks = <0x00000002>; compatible = "xlnx,microblaze-9.5"; d-cache-baseaddr = <0x80000000>; d-cache-highaddr = <0x8fffffff>; d-cache-line-size = <0x00000020>; d-cache-size = <0x00004000>; device_type = "cpu"; i-cache-baseaddr = <0x80000000>; i-cache-highaddr = <0x8fffffff>; i-cache-line-size = <0x00000010>; i-cache-size = <0x00004000>; interrupt-handle = <0x00000003>; model = "microblaze,9.5"; timebase-frequency = <0x05f5e100>; xlnx,addr-tag-bits = <0x00000010>; xlnx,allow-dcache-wr = <0x00000001>; xlnx,allow-icache-wr = <0x00000001>; xlnx,area-optimized = <0x00000000>; xlnx,async-interrupt = <0x00000001>; xlnx,avoid-primitives = <0x00000000>; xlnx,base-vectors = <0x00000000>; xlnx,branch-target-cache-size = <0x00000000>; xlnx,cache-byte-size = <0x00004000>; xlnx,d-axi = <0x00000001>; xlnx,d-lmb = <0x00000001>; xlnx,d-lmb-mon = <0x00000000>; xlnx,data-size = <0x00000020>; xlnx,dc-axi-mon = <0x00000000>; xlnx,dcache-addr-tag = <0x00000010>; xlnx,dcache-always-used = <0x00000001>; xlnx,dcache-byte-size = <0x00004000>; xlnx,dcache-data-width = <0x00000000>; xlnx,dcache-force-tag-lutram = <0x00000000>; xlnx,dcache-line-len = <0x00000008>; xlnx,dcache-use-writeback = <0x00000000>; xlnx,dcache-victims = <0x00000000>; xlnx,debug-counter-width = <0x00000020>; xlnx,debug-enabled = <0x00000001>; xlnx,debug-event-counters = <0x00000005>; xlnx,debug-external-trace = <0x00000000>; xlnx,debug-latency-counters = <0x00000001>; xlnx,debug-profile-size = <0x00000000>; xlnx,debug-trace-size = <0x00002000>; xlnx,div-zero-exception = <0x00000001>; xlnx,dp-axi-mon = <0x00000000>; xlnx,dynamic-bus-sizing = <0x00000000>; xlnx,ecc-use-ce-exception = <0x00000000>; xlnx,edge-is-positive = <0x00000001>; xlnx,enable-discrete-ports = <0x00000000>; xlnx,endianness = <0x00000001>; xlnx,fault-tolerant = <0x00000000>; xlnx,fpu-exception = <0x00000000>; xlnx,freq = <0x05f5e100>; xlnx,fsl-exception = <0x00000000>; xlnx,fsl-links = <0x00000000>; xlnx,i-axi = <0x00000000>; xlnx,i-lmb = <0x00000001>; xlnx,i-lmb-mon = <0x00000000>; xlnx,ic-axi-mon = <0x00000000>; xlnx,icache-always-used = <0x00000001>; xlnx,icache-data-width = <0x00000000>; xlnx,icache-force-tag-lutram = <0x00000000>; xlnx,icache-line-len = <0x00000004>; xlnx,icache-streams = <0x00000001>; xlnx,icache-victims = <0x00000008>; xlnx,ill-opcode-exception = <0x00000001>; xlnx,imprecise-exceptions = <0x00000000>; xlnx,interconnect = <0x00000002>; xlnx,interrupt-is-edge = <0x00000000>; xlnx,interrupt-mon = <0x00000000>; xlnx,ip-axi-mon = <0x00000000>; xlnx,lockstep-select = <0x00000000>; xlnx,lockstep-slave = <0x00000000>; xlnx,mmu-dtlb-size = <0x00000004>; xlnx,mmu-itlb-size = <0x00000002>; xlnx,mmu-privileged-instr = <0x00000000>; xlnx,mmu-tlb-access = <0x00000003>; xlnx,mmu-zones = <0x00000002>; xlnx,num-sync-ff-clk = <0x00000002>; xlnx,num-sync-ff-clk-debug = <0x00000002>; xlnx,num-sync-ff-clk-irq = <0x00000001>; xlnx,num-sync-ff-dbg-clk = <0x00000001>; xlnx,number-of-pc-brk = <0x00000001>; xlnx,number-of-rd-addr-brk = <0x00000000>; xlnx,number-of-wr-addr-brk = <0x00000000>; xlnx,opcode-0x0-illegal = <0x00000001>; xlnx,optimization = <0x00000000>; xlnx,pc-width = <0x00000020>; xlnx,pvr = <0x00000002>; xlnx,pvr-user1 = <0x00000000>; xlnx,pvr-user2 = <0x00000000>; xlnx,reset-msr = <0x00000000>; xlnx,sco = <0x00000000>; xlnx,trace = <0x00000000>; xlnx,unaligned-exceptions = <0x00000001>; xlnx,use-barrel = <0x00000001>; xlnx,use-branch-target-cache = <0x00000001>; xlnx,use-config-reset = <0x00000000>; xlnx,use-dcache = <0x00000001>; xlnx,use-div = <0x00000001>; xlnx,use-ext-brk = <0x00000000>; xlnx,use-ext-nm-brk = <0x00000000>; xlnx,use-extended-fsl-instr = <0x00000000>; xlnx,use-fpu = <0x00000000>; xlnx,use-hw-mul = <0x00000002>; xlnx,use-icache = <0x00000001>; xlnx,use-interrupt = <0x00000002>; xlnx,use-mmu = <0x00000003>; xlnx,use-msr-instr = <0x00000001>; xlnx,use-pcmp-instr = <0x00000001>; xlnx,use-reorder-instr = <0x00000001>; xlnx,use-stack-protection = <0x00000000>; }; }; clocks { #address-cells = <0x00000001>; #size-cells = <0x00000000>; clk_cpu@0 { #clock-cells = <0x00000000>; clock-frequency = <0x05f5e100>; clock-output-names = "clk_cpu"; compatible = "fixed-clock"; reg = <0x00000000>; linux,phandle = <0x00000002>; phandle = <0x00000002>; }; clk_bus_0@1 { #clock-cells = <0x00000000>; clock-frequency = <0x05f5e100>; clock-output-names = "clk_bus_0"; compatible = "fixed-clock"; reg = <0x00000001>; }; }; amba_pl { #address-cells = <0x00000001>; #size-cells = <0x00000001>; compatible = "simple-bus"; ranges; linux,phandle = <0x00000001>; phandle = <0x00000001>; interrupt-controller@41200000 { #interrupt-cells = <0x00000002>; compatible = "xlnx,xps-intc-1.00.a"; interrupt-controller; reg = <0x41200000 0x00010000>; xlnx,kind-of-intr = <0x00000001>; xlnx,num-intr-inputs = <0x00000003>; linux,phandle = <0x00000003>; phandle = <0x00000003>; }; serial@40600000 { clock-frequency = <0x05f5e100>; compatible = "xlnx,xps-uartlite-1.00.a"; current-speed = <0x0001c200>; }; axi_quad_spi@44a10000 { compatible = "xlnx,xps-spi-2.00.a"; interrupt-parent = <0x00000003>; interrupts = <0x00000000 0x00000000>; reg = <0x44a00000 0x00010000>; xlnx,num-ss-bits = <0x00000001>; #address-cells = <0x00000001>; #size-cells = <0x00000000>; flash@0 { compatible = "micron,n25q256a13"; reg = <0x00000000>; #address-cells = <0x00000001>; #size-cells = <0x00000001>; spi-max-frequency = <0x017d7840>; partition@0x00000000 { label = "fpga"; reg = <0x00000000 0x00a00000>; }; partition@0x00a00000 { label = "boot"; reg = <0x00a00000 0x00060000>; }; partition@0x00a60000 { label = "bootenv"; reg = <0x00a60000 0x00040000>; }; partition@0x00aa0000 { label = "kernel"; reg = <0x00aa0000 0x00c00000>; }; partition@0x016a0000 { label = "spare"; reg = <0x016a0000 0x00000000>; }; }; }; }; aliases { serial0 = "/amba_pl/serial@40600000"; spi0 = "/amba_pl/axi_quad_spi@44a10000"; }; chosen { bootargs = "console=ttyUL0,115200 earlyprintk"; }; memory { device_type = "memory"; reg = <0x80000000 0x10000000>; }; }; Any hints how to debug this further? Marco diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts index 2033309..8751c36 100644 --- a/arch/microblaze/dts/microblaze-generic.dts +++ b/arch/microblaze/dts/microblaze-generic.dts @@ -1,7 +1,13 @@ -/dts-v1/; -/ { - #address-cells = <1>; - #size-cells = <1>; - aliases { - } ; -} ; +/dts-v1/; +/include/ "system-conf.dtsi" +/ { +}; + + +&spi_flash { + flash0: flash@0 { + compatible = "micron,n25q256a13"; + }; +}; + + diff --git a/arch/microblaze/dts/pl.dtsi b/arch/microblaze/dts/pl.dtsi new file mode 100644 index 0000000..1511a15 --- /dev/null +++ b/arch/microblaze/dts/pl.dtsi @@ -0,0 +1,178 @@ +/* + * CAUTION: This file is automatically generated by Xilinx. + * Version: HSI 2015.4 + * Today is: Tue Oct 27 09:36:05 2015 +*/ + + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,microblaze"; + model = "Xilinx MicroBlaze"; + cpus { + #address-cells = <1>; + #cpus = <1>; + #size-cells = <0>; + microblaze_0: cpu@0 { + bus-handle = <&amba_pl>; + clock-frequency = <100000000>; + clocks = <&clk_cpu>; + compatible = "xlnx,microblaze-9.5"; + d-cache-baseaddr = <0x80000000>; + d-cache-highaddr = <0x8fffffff>; + d-cache-line-size = <0x20>; + d-cache-size = <0x4000>; + device_type = "cpu"; + i-cache-baseaddr = <0x80000000>; + i-cache-highaddr = <0x8fffffff>; + i-cache-line-size = <0x10>; + i-cache-size = <0x4000>; + interrupt-handle = <µblaze_0_axi_intc>; + model = "microblaze,9.5"; + timebase-frequency = <100000000>; + xlnx,addr-tag-bits = <0x10>; + xlnx,allow-dcache-wr = <0x1>; + xlnx,allow-icache-wr = <0x1>; + xlnx,area-optimized = <0x0>; + xlnx,async-interrupt = <0x1>; + xlnx,avoid-primitives = <0x0>; + xlnx,base-vectors = <0x00000000>; + xlnx,branch-target-cache-size = <0x0>; + xlnx,cache-byte-size = <0x4000>; + xlnx,d-axi = <0x1>; + xlnx,d-lmb = <0x1>; + xlnx,d-lmb-mon = <0x0>; + xlnx,data-size = <0x20>; + xlnx,dc-axi-mon = <0x0>; + xlnx,dcache-addr-tag = <0x10>; + xlnx,dcache-always-used = <0x1>; + xlnx,dcache-byte-size = <0x4000>; + xlnx,dcache-data-width = <0x0>; + xlnx,dcache-force-tag-lutram = <0x0>; + xlnx,dcache-line-len = <0x8>; + xlnx,dcache-use-writeback = <0x0>; + xlnx,dcache-victims = <0x0>; + xlnx,debug-counter-width = <0x20>; + xlnx,debug-enabled = <0x1>; + xlnx,debug-event-counters = <0x5>; + xlnx,debug-external-trace = <0x0>; + xlnx,debug-latency-counters = <0x1>; + xlnx,debug-profile-size = <0x0>; + xlnx,debug-trace-size = <0x2000>; + xlnx,div-zero-exception = <0x1>; + xlnx,dp-axi-mon = <0x0>; + xlnx,dynamic-bus-sizing = <0x0>; + xlnx,ecc-use-ce-exception = <0x0>; + xlnx,edge-is-positive = <0x1>; + xlnx,enable-discrete-ports = <0x0>; + xlnx,endianness = <0x1>; + xlnx,fault-tolerant = <0x0>; + xlnx,fpu-exception = <0x0>; + xlnx,freq = <0x5f5e100>; + xlnx,fsl-exception = <0x0>; + xlnx,fsl-links = <0x0>; + xlnx,i-axi = <0x0>; + xlnx,i-lmb = <0x1>; + xlnx,i-lmb-mon = <0x0>; + xlnx,ic-axi-mon = <0x0>; + xlnx,icache-always-used = <0x1>; + xlnx,icache-data-width = <0x0>; + xlnx,icache-force-tag-lutram = <0x0>; + xlnx,icache-line-len = <0x4>; + xlnx,icache-streams = <0x1>; + xlnx,icache-victims = <0x8>; + xlnx,ill-opcode-exception = <0x1>; + xlnx,imprecise-exceptions = <0x0>; + xlnx,interconnect = <0x2>; + xlnx,interrupt-is-edge = <0x0>; + xlnx,interrupt-mon = <0x0>; + xlnx,ip-axi-mon = <0x0>; + xlnx,lockstep-select = <0x0>; + xlnx,lockstep-slave = <0x0>; + xlnx,mmu-dtlb-size = <0x4>; + xlnx,mmu-itlb-size = <0x2>; + xlnx,mmu-privileged-instr = <0x0>; + xlnx,mmu-tlb-access = <0x3>; + xlnx,mmu-zones = <0x2>; + xlnx,num-sync-ff-clk = <0x2>; + xlnx,num-sync-ff-clk-debug = <0x2>; + xlnx,num-sync-ff-clk-irq = <0x1>; + xlnx,num-sync-ff-dbg-clk = <0x1>; + xlnx,number-of-pc-brk = <0x1>; + xlnx,number-of-rd-addr-brk = <0x0>; + xlnx,number-of-wr-addr-brk = <0x0>; + xlnx,opcode-0x0-illegal = <0x1>; + xlnx,optimization = <0x0>; + xlnx,pc-width = <0x20>; + xlnx,pvr = <0x2>; + xlnx,pvr-user1 = <0x00>; + xlnx,pvr-user2 = <0x00000000>; + xlnx,reset-msr = <0x00000000>; + xlnx,sco = <0x0>; + xlnx,trace = <0x0>; + xlnx,unaligned-exceptions = <0x1>; + xlnx,use-barrel = <0x1>; + xlnx,use-branch-target-cache = <0x1>; + xlnx,use-config-reset = <0x0>; + xlnx,use-dcache = <0x1>; + xlnx,use-div = <0x1>; + xlnx,use-ext-brk = <0x0>; + xlnx,use-ext-nm-brk = <0x0>; + xlnx,use-extended-fsl-instr = <0x0>; + xlnx,use-fpu = <0x0>; + xlnx,use-hw-mul = <0x2>; + xlnx,use-icache = <0x1>; + xlnx,use-interrupt = <0x2>; + xlnx,use-mmu = <0x3>; + xlnx,use-msr-instr = <0x1>; + xlnx,use-pcmp-instr = <0x1>; + xlnx,use-reorder-instr = <0x1>; + xlnx,use-stack-protection = <0x0>; + }; + }; + clocks { + #address-cells = <1>; + #size-cells = <0>; + clk_cpu: clk_cpu@0 { + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "clk_cpu"; + compatible = "fixed-clock"; + reg = <0>; + }; + clk_bus_0: clk_bus_0@1 { + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "clk_bus_0"; + compatible = "fixed-clock"; + reg = <1>; + }; + }; + amba_pl: amba_pl { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges ; + microblaze_0_axi_intc: interrupt-controller@41200000 { + #interrupt-cells = <2>; + compatible = "xlnx,xps-intc-1.00.a"; + interrupt-controller ; + reg = <0x41200000 0x10000>; + xlnx,kind-of-intr = <0x1>; + xlnx,num-intr-inputs = <0x3>; + }; + RS232_Uart_1: serial@40600000 { + clock-frequency = <100000000>; + compatible = "xlnx,xps-uartlite-1.00.a"; + current-speed = <115200>; + } ; + spi_flash: axi_quad_spi@44a10000 { + compatible = "xlnx,xps-spi-2.00.a"; + interrupt-parent = <µblaze_0_axi_intc>; + interrupts = <0 0>; + reg = <0x44a00000 0x10000>; + xlnx,num-ss-bits = <0x1>; + }; + }; +}; diff --git a/arch/microblaze/dts/system-conf.dtsi b/arch/microblaze/dts/system-conf.dtsi new file mode 100644 index 0000000..2aad1ab --- /dev/null +++ b/arch/microblaze/dts/system-conf.dtsi @@ -0,0 +1,55 @@ +/* + * CAUTION: This file is automatically generated by PetaLinux SDK. + * DO NOT modify this file + */ + +/include/ "pl.dtsi" + +/ { + model = "Xilinx-AC701-AXI-full-2015.4"; + aliases { + serial0 = &RS232_Uart_1; + spi0 = &spi_flash; + }; + chosen { + bootargs = "console=ttyUL0,115200 earlyprintk"; + }; + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + + +&spi_flash { + #address-cells = <1>; + #size-cells = <0>; + flash0: flash@0 { + compatible = "micron,n25q128"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <25000000>; + partition@0x00000000 { + label = "fpga"; + reg = <0x00000000 0x00a00000>; + }; + partition@0x00a00000 { + label = "boot"; + reg = <0x00a00000 0x00060000>; + }; + partition@0x00a60000 { + label = "bootenv"; + reg = <0x00a60000 0x00040000>; + }; + partition@0x00aa0000 { + label = "kernel"; + reg = <0x00aa0000 0x00c00000>; + }; + partition@0x016a0000 { + label = "spare"; + reg = <0x016a0000 0x00000000>; + }; + }; +}; + diff --git a/arch/microblaze/dts/system-top.dts b/arch/microblaze/dts/system-top.dts new file mode 100644 index 0000000..3832812 --- /dev/null +++ b/arch/microblaze/dts/system-top.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/include/ "system-conf.dtsi" +/ { +}; + +s +&spi_flash { + flash0: flash@0 { + compatible = "micron,n25q256a13"; + }; +}; + + diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk index 36bdd96..26a21bf 100644 --- a/board/xilinx/microblaze-generic/config.mk +++ b/board/xilinx/microblaze-generic/config.mk @@ -1,18 +1,10 @@ -# -# (C) Copyright 2007 Michal Simek -# -# Michal SIMEK -# -# SPDX-License-Identifier: GPL-2.0+ -# -# CAUTION: This file is a faked configuration !!! -# There is no real target for the microblaze-generic -# configuration. You have to replace this file with -# the generated file from your Xilinx design flow. -# - -CONFIG_SYS_TEXT_BASE = 0x29000000 - -PLATFORM_CPPFLAGS += -mno-xl-soft-mul -PLATFORM_CPPFLAGS += -mno-xl-soft-div -PLATFORM_CPPFLAGS += -mxl-barrel-shift +# +# CAUTION: This file is automatically generated by PetaLinux SDK +# + +TEXT_BASE = 0x80400000 +CONFIG_SYS_TEXT_BASE = 0x80400000 + +PLATFORM_CPPFLAGS += -mno-xl-soft-mul +PLATFORM_CPPFLAGS += -mno-xl-soft-div +PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h deleted file mode 100644 index d6d0d67..0000000 --- a/board/xilinx/microblaze-generic/xparameters.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * SPDX-License-Identifier: GPL-2.0+ - * - * CAUTION: This file is a faked configuration !!! - * There is no real target for the microblaze-generic - * configuration. You have to replace this file with - * the generated file from your Xilinx design flow. - */ - -#define XILINX_BOARD_NAME microblaze-generic - -/* System Clock Frequency */ -#define XILINX_CLOCK_FREQ 100000000 - -/* Microblaze is microblaze_0 */ -#define XILINX_USE_MSR_INSTR 1 -#define XILINX_FSL_NUMBER 3 - -/* Interrupt controller is opb_intc_0 */ -#define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 6 - -/* Timer pheriphery is opb_timer_1 */ -#define XILINX_TIMER_BASEADDR 0x41c00000 -#define XILINX_TIMER_IRQ 0 - -/* Uart pheriphery is RS232_Uart */ -#define XILINX_UARTLITE_BASEADDR 0x40600000 -#define XILINX_UARTLITE_BAUDRATE 115200 - -/* IIC pheriphery is IIC_EEPROM */ -#define XILINX_IIC_0_BASEADDR 0x40800000 -#define XILINX_IIC_0_FREQ 100000 -#define XILINX_IIC_0_BIT 0 - -/* GPIO is LEDs_4Bit*/ -#define XILINX_GPIO_BASEADDR 0x40000000 - -/* Flash Memory is FLASH_2Mx32 */ -#define XILINX_FLASH_START 0x2c000000 -#define XILINX_FLASH_SIZE 0x00800000 - -/* Main Memory is DDR_SDRAM_64Mx32 */ -#define XILINX_RAM_START 0x28000000 -#define XILINX_RAM_SIZE 0x04000000 - -/* Sysace Controller is SysACE_CompactFlash */ -#define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180ffff -#define XILINX_SYSACE_MEM_WIDTH 16 - -/* Ethernet controller is Ethernet_MAC */ -#define XILINX_EMACLITE_BASEADDR 0x40C00000 - -/* LL_TEMAC Ethernet controller */ -#define XILINX_LLTEMAC_BASEADDR 0x44000000 -#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180 -#define XILINX_LLTEMAC_BASEADDR1 0x44200000 -#define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000 - -/* Watchdog IP is wxi_timebase_wdt_0 */ -#define XILINX_WATCHDOG_BASEADDR 0x50000000 -#define XILINX_WATCHDOG_IRQ 1 diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index da589a0..485a723 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -1,8 +1,280 @@ +# +# Automatically generated file; DO NOT EDIT. +# U-Boot 2015.07 Configuration +# +CONFIG_HAVE_GENERIC_BOARD=y +CONFIG_SYS_GENERIC_BOARD=y +# CONFIG_ARC is not set +# CONFIG_ARM is not set +# CONFIG_AVR32 is not set +# CONFIG_BLACKFIN is not set +# CONFIG_M68K is not set CONFIG_MICROBLAZE=y +# CONFIG_MIPS is not set +# CONFIG_NDS32 is not set +# CONFIG_NIOS2 is not set +# CONFIG_OPENRISC is not set +# CONFIG_PPC is not set +# CONFIG_SANDBOX is not set +# CONFIG_SH is not set +# CONFIG_SPARC is not set +# CONFIG_X86 is not set +CONFIG_SYS_ARCH="microblaze" +CONFIG_SYS_VENDOR="xilinx" +CONFIG_SYS_BOARD="microblaze-generic" +CONFIG_SYS_CONFIG_NAME="microblaze-generic" + +# +# MicroBlaze architecture +# CONFIG_TARGET_MICROBLAZE_GENERIC=y CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" -CONFIG_SPL=y -CONFIG_SYS_PROMPT="U-Boot-mONStR> " + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_EXPERT=y +CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y + +# +# Boot images +# +CONFIG_SUPPORT_SPL=y +# CONFIG_SPL is not set +# CONFIG_FIT is not set +CONFIG_SYS_EXTRA_OPTIONS="" + +# +# Command line interface +# +# CONFIG_HUSH_PARSER is not set + +# +# Autoboot options +# +# CONFIG_AUTOBOOT_KEYED is not set + +# +# Commands +# + +# +# Info commands +# +CONFIG_CMD_BDI=y +CONFIG_CMD_CONSOLE=y +# CONFIG_CMD_CPU is not set +# CONFIG_CMD_LICENSE is not set + +# +# Boot commands +# +CONFIG_CMD_BOOTD=y +CONFIG_CMD_BOOTM=y +CONFIG_CMD_GO=y +CONFIG_CMD_RUN=y +CONFIG_CMD_IMI=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_XIMG=y + +# +# Environment commands +# +CONFIG_CMD_EXPORTENV=y +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_EDITENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_ENV_EXISTS=y + +# +# Memory commands +# +CONFIG_CMD_MEMORY=y +CONFIG_CMD_CRC32=y +# CONFIG_LOOPW is not set +# CONFIG_CMD_MEMTEST is not set +# CONFIG_CMD_MX_CYCLIC is not set +# CONFIG_CMD_MEMINFO is not set + +# +# Device access commands +# +CONFIG_CMD_DM=y +# CONFIG_CMD_DEMO is not set +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_NAND is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_I2C is not set +# CONFIG_CMD_USB is not set +CONFIG_CMD_FPGA=y + +# +# Shell scripting commands +# +CONFIG_CMD_ECHO=y +CONFIG_CMD_ITEST=y +CONFIG_CMD_SOURCE=y # CONFIG_CMD_SETEXPR is not set + +# +# Network commands +# +CONFIG_CMD_NET=y +# CONFIG_CMD_TFTPPUT is not set +# CONFIG_CMD_TFTPSRV is not set +# CONFIG_CMD_RARP is not set +# CONFIG_CMD_DHCP is not set +CONFIG_CMD_NFS=y +CONFIG_CMD_PING=y +# CONFIG_CMD_CDP is not set +# CONFIG_CMD_SNTP is not set +# CONFIG_CMD_DNS is not set +# CONFIG_CMD_LINK_LOCAL is not set + +# +# Misc commands +# +# CONFIG_CMD_TIME is not set +CONFIG_CMD_MISC=y +# CONFIG_CMD_TIMER is not set +# CONFIG_CMD_ZYNQ_RSA is not set + +# +# Boot timing +# +# CONFIG_BOOTSTAGE is not set +CONFIG_BOOTSTAGE_USER_COUNT=20 +CONFIG_BOOTSTAGE_STASH_ADDR=0 +CONFIG_BOOTSTAGE_STASH_SIZE=4096 + +# +# Power commands +# +CONFIG_SUPPORT_OF_CONTROL=y + +# +# Device Tree Control +# CONFIG_OF_CONTROL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y +# CONFIG_OF_SEPARATE is not set CONFIG_OF_EMBED=y +CONFIG_NET=y +# CONFIG_NET_RANDOM_ETHADDR is not set + +# +# Device Drivers +# +CONFIG_DM=y +CONFIG_DM_WARN=y +CONFIG_DM_DEVICE_REMOVE=y +CONFIG_DM_STDIO=y +CONFIG_DM_SEQ_ALIAS=y +# CONFIG_CPU is not set +# CONFIG_DM_DEMO is not set + +# +# PCI +# +# CONFIG_DM_PCI is not set + +# +# NAND Device Support +# +# CONFIG_NAND_DENALI is not set +# CONFIG_NAND_VF610_NFC is not set + +# +# Generic NAND options +# + +# +# SPI Flash Support +# +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +# CONFIG_SPI_FLASH_DATAFLASH is not set +# CONFIG_SPI_FLASH_MTD is not set +# CONFIG_CROS_EC is not set +# CONFIG_CONFIG_FSL_SEC_MON is not set +# CONFIG_PCA9551_LED is not set +# CONFIG_DM_ETH is not set +# CONFIG_NETDEVICES is not set +# CONFIG_CROS_EC_KEYB is not set +# CONFIG_DM_SERIAL is not set +# CONFIG_DEBUG_UART is not set +# CONFIG_TPM_TIS_SANDBOX is not set +# CONFIG_DM_I2C is not set +# CONFIG_DM_I2C_COMPAT is not set + +# +# SPI Support +# +CONFIG_DM_SPI=y +# CONFIG_CADENCE_QSPI is not set +# CONFIG_DESIGNWARE_SPI is not set +# CONFIG_EXYNOS_SPI is not set +# CONFIG_FSL_DSPI is not set +# CONFIG_FSL_QSPI is not set +# CONFIG_ICH_SPI is not set +# CONFIG_TEGRA114_SPI is not set +# CONFIG_TEGRA20_SFLASH is not set +# CONFIG_TEGRA20_SLINK is not set +# CONFIG_XILINX_SPI is not set +# CONFIG_FSL_ESPI is not set +# CONFIG_TI_QSPI is not set +# CONFIG_DM_GPIO is not set +# CONFIG_LPC32XX_GPIO is not set +# CONFIG_VYBRID_GPIO is not set + +# +# Power +# +# CONFIG_DM_PMIC is not set +# CONFIG_DM_REGULATOR is not set +# CONFIG_VIDEO_VESA is not set +# CONFIG_VIDEO_LCD_SSD2828 is not set +# CONFIG_DISPLAY_PORT is not set +# CONFIG_VIDEO_TEGRA124 is not set +# CONFIG_SOUND is not set +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB is not set + +# +# MMC Host controller Support +# +# CONFIG_DM_RTC is not set +# CONFIG_FSL_CAAM is not set +# CONFIG_DM_THERMAL is not set +# CONFIG_PHYS_TO_BUS is not set + +# +# File systems +# + +# +# Library routines +# +# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set +CONFIG_SYS_HZ=1000 +# CONFIG_SYS_VSNPRINTF is not set +CONFIG_REGEX=y +# CONFIG_LIB_RAND is not set +# CONFIG_RSA is not set + +# +# Hashing Support +# +# CONFIG_SHA1 is not set +# CONFIG_SHA256 is not set +# CONFIG_SHA_HW_ACCEL is not set +# CONFIG_ERRNO_STR is not set +# CONFIG_UNIT_TEST is not set diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 8ce1c49..264eaa5 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -1,434 +1,4 @@ -/* - * (C) Copyright 2007-2010 Michal Simek - * - * Michal SIMEK - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "../board/xilinx/microblaze-generic/xparameters.h" - -/* MicroBlaze CPU */ -#define MICROBLAZE_V5 1 - -/* linear and spi flash memory */ -#ifdef XILINX_FLASH_START -#define FLASH -#undef SPIFLASH -#undef RAMENV /* hold environment in flash */ -#else -#ifdef XILINX_SPI_FLASH_BASEADDR -#undef FLASH -#define SPIFLASH -#undef RAMENV /* hold environment in flash */ -#else -#undef FLASH -#undef SPIFLASH -#define RAMENV /* hold environment in RAM */ -#endif -#endif - -/* uart */ -#ifdef XILINX_UARTLITE_BASEADDR -# define CONFIG_XILINX_UARTLITE -# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR -# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE -# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } -# define CONSOLE_ARG "console=console=ttyUL0,115200\0" -#elif XILINX_UART16550_BASEADDR -# define CONFIG_SYS_NS16550 1 -# define CONFIG_SYS_NS16550_SERIAL -# if defined(__MICROBLAZEEL__) -# define CONFIG_SYS_NS16550_REG_SIZE -4 -# else -# define CONFIG_SYS_NS16550_REG_SIZE 4 -# endif -# define CONFIG_CONS_INDEX 1 -# define CONFIG_SYS_NS16550_COM1 \ - ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) -# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ -# define CONFIG_BAUDRATE 115200 - -/* The following table includes the supported baudrates */ -# define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -# define CONSOLE_ARG "console=console=ttyS0,115200\0" -#else -# error Undefined uart -#endif - -/* setting reset address */ -/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ - -/* ethernet */ -#undef CONFIG_SYS_ENET -#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL) -# define CONFIG_XILINX_EMACLITE 1 -# define CONFIG_SYS_ENET -#endif -#if defined(XILINX_LLTEMAC_BASEADDR) -# define CONFIG_XILINX_LL_TEMAC 1 -# define CONFIG_SYS_ENET -#endif -#if defined(XILINX_AXIEMAC_BASEADDR) -# define CONFIG_XILINX_AXIEMAC 1 -# define CONFIG_SYS_ENET -#endif - -#undef ET_DEBUG - -/* gpio */ -#ifdef XILINX_GPIO_BASEADDR -# define CONFIG_XILINX_GPIO -# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR -#endif - -/* interrupt controller */ -#ifdef XILINX_INTC_BASEADDR -# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR -# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS -#endif - -/* timer */ -#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ) -# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR -# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ -#endif - -/* watchdog */ -#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) -# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR -# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ -# define CONFIG_HW_WATCHDOG -# define CONFIG_XILINX_TB_WATCHDOG -#endif - -#if !defined(CONFIG_OF_CONTROL) || \ - (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL)) -/* ddr sdram - main memory */ -# define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START -# define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE -#endif - -#define CONFIG_SYS_MALLOC_LEN 0xC0000 -#ifndef CONFIG_SPL_BUILD -# define CONFIG_SYS_MALLOC_F_LEN 1024 -#else -# define CONFIG_SYS_MALLOC_SIMPLE -# define CONFIG_SYS_MALLOC_F_LEN 0x150 -#endif - -/* Stack location before relocation */ -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_TEXT_BASE - -/* - * CFI flash memory layout - Example - * CONFIG_SYS_FLASH_BASE = 0x2200_0000; - * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB - * - * SECT_SIZE = 0x20000; 128kB is one sector - * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store - * - * 0x2200_0000 CONFIG_SYS_FLASH_BASE - * FREE 256kB - * 0x2204_0000 CONFIG_ENV_ADDR - * ENV_AREA 128kB - * 0x2206_0000 - * FREE - * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - * - */ - -#ifdef FLASH -# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START -# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE -# define CONFIG_SYS_FLASH_CFI 1 -# define CONFIG_FLASH_CFI_DRIVER 1 -/* ?empty sector */ -# define CONFIG_SYS_FLASH_EMPTY_INFO 1 -/* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -# define CONFIG_SYS_MAX_FLASH_SECT 512 -/* hardware flash protection */ -# define CONFIG_SYS_FLASH_PROTECTION -/* use buffered writes (20x faster) */ -# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -# ifdef RAMENV -# define CONFIG_ENV_IS_NOWHERE 1 -# define CONFIG_ENV_SIZE 0x1000 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - -# else /* FLASH && !RAMENV */ -# define CONFIG_ENV_IS_IN_FLASH 1 -/* 128K(one sector) for env */ -# define CONFIG_ENV_SECT_SIZE 0x20000 -# define CONFIG_ENV_ADDR \ - (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) -# define CONFIG_ENV_SIZE 0x20000 -# endif /* FLASH && !RAMBOOT */ -#else /* !FLASH */ - -#ifdef SPIFLASH -# define CONFIG_SYS_NO_FLASH 1 -# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR -# define CONFIG_XILINX_SPI 1 -# define CONFIG_SPI 1 -# define CONFIG_SPI_FLASH_STMICRO 1 -# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 -# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ -# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS - -# ifdef RAMENV -# define CONFIG_ENV_IS_NOWHERE 1 -# define CONFIG_ENV_SIZE 0x1000 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - -# else /* SPIFLASH && !RAMENV */ -# define CONFIG_ENV_IS_IN_SPI_FLASH 1 -# define CONFIG_ENV_SPI_MODE SPI_MODE_3 -# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -/* 128K(two sectors) for env */ -# define CONFIG_ENV_SECT_SIZE 0x10000 -# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE) -/* Warning: adjust the offset in respect of other flash content and size */ -# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */ -# endif /* SPIFLASH && !RAMBOOT */ -#else /* !SPIFLASH */ - -/* ENV in RAM */ -# define CONFIG_SYS_NO_FLASH 1 -# define CONFIG_ENV_IS_NOWHERE 1 -# define CONFIG_ENV_SIZE 0x1000 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) -#endif /* !SPIFLASH */ -#endif /* !FLASH */ - -/* system ace */ -#ifdef XILINX_SYSACE_BASEADDR -# define CONFIG_SYSTEMACE -/* #define DEBUG_SYSTEMACE */ -# define SYSTEMACE_CONFIG_FPGA -# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR -# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH -# define CONFIG_DOS_PARTITION -#endif - -#if defined(XILINX_USE_ICACHE) -# define CONFIG_ICACHE -#else -# undef CONFIG_ICACHE -#endif - -#if defined(XILINX_USE_DCACHE) -# define CONFIG_DCACHE -#else -# undef CONFIG_DCACHE -#endif - -#ifndef XILINX_DCACHE_BYTE_SIZE -#define XILINX_DCACHE_BYTE_SIZE 32768 -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MFSL -#define CONFIG_CMD_GPIO - -#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) -# define CONFIG_CMD_CACHE -#else -# undef CONFIG_CMD_CACHE -#endif - -#ifdef CONFIG_SYS_ENET -# define CONFIG_CMD_PING -# define CONFIG_CMD_DHCP -# define CONFIG_CMD_TFTPPUT -#endif - -#if defined(CONFIG_SYSTEMACE) -# define CONFIG_CMD_EXT2 -# define CONFIG_CMD_FAT -#endif - -#if defined(FLASH) -# define CONFIG_CMD_JFFS2 -# define CONFIG_CMD_UBI -# undef CONFIG_CMD_UBIFS - -# if !defined(RAMENV) -# define CONFIG_CMD_SAVES -# endif - -#else -#if defined(SPIFLASH) -# define CONFIG_CMD_SF - -# if !defined(RAMENV) -# define CONFIG_CMD_SAVES -# endif -#else -# undef CONFIG_CMD_JFFS2 -# undef CONFIG_CMD_UBI -# undef CONFIG_CMD_UBIFS -#endif -#endif - -#if defined(CONFIG_CMD_JFFS2) -# define CONFIG_MTD_PARTITIONS -#endif - -#if defined(CONFIG_CMD_UBIFS) -# define CONFIG_CMD_UBI -# define CONFIG_LZO -#endif - -#if defined(CONFIG_CMD_UBI) -# define CONFIG_MTD_PARTITIONS -# define CONFIG_RBTREE -#endif - -#if defined(CONFIG_MTD_PARTITIONS) -/* MTD partitions */ -#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */ -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=flash-0" - -/* default mtd partition table */ -#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\ - "256k(env),3m(kernel),1m(romfs),"\ - "1m(cramfs),-(jffs2)" -#endif - -/* size of console buffer */ -#define CONFIG_SYS_CBSIZE 512 - /* print buffer size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 15 -#define CONFIG_SYS_LONGHELP -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START - -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ -#define CONFIG_BOOTARGS "root=romfs" -#define CONFIG_HOSTNAME XILINX_BOARD_NAME -#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" -#define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.5 -#define CONFIG_GATEWAYIP 192.168.0.1 - -/* architecture dependent code */ -#define CONFIG_SYS_USR_EXCEP /* user exception */ - -#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" - -#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ - "nor0=flash-0\0"\ - "mtdparts=mtdparts=flash-0:"\ - "256k(u-boot),256k(env),3m(kernel),"\ - "1m(romfs),1m(cramfs),-(jffs2)\0"\ - "nc=setenv stdout nc;"\ - "setenv stdin nc\0" \ - "serial=setenv stdout serial;"\ - "setenv stdin serial\0" - -#define CONFIG_CMDLINE_EDITING - -#define CONFIG_NETCONSOLE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* Enable flat device tree support */ -#define CONFIG_LMB 1 -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 - -#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC) -# define CONFIG_MII 1 -# define CONFIG_CMD_MII 1 -# define CONFIG_PHY_GIGE 1 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 -# define CONFIG_PHYLIB 1 -# define CONFIG_PHY_ATHEROS 1 -# define CONFIG_PHY_BROADCOM 1 -# define CONFIG_PHY_DAVICOM 1 -# define CONFIG_PHY_LXT 1 -# define CONFIG_PHY_MARVELL 1 -# define CONFIG_PHY_MICREL 1 -# define CONFIG_PHY_NATSEMI 1 -# define CONFIG_PHY_REALTEK 1 -# define CONFIG_PHY_VITESSE 1 -#else -# undef CONFIG_MII -# undef CONFIG_CMD_MII -# undef CONFIG_PHYLIB -#endif - -/* SPL part */ -#define CONFIG_CMD_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_BOARD_INIT - -#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" - -#define CONFIG_SPL_RAM_DEVICE -#ifdef CONFIG_SYS_FLASH_BASE -# define CONFIG_SPL_NOR_SUPPORT -# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE -#endif - -/* for booting directly linux */ -#define CONFIG_SPL_OS_BOOT - -#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \ - 0x60000) -#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ - 0x40000) -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ - 0x1000000) - -/* SP location before relocation, must use scratch RAM */ -/* BRAM start */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x0 -/* BRAM size - will be generated */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 - -# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_MALLOC_F_LEN) - -/* Just for sure that there is a space for stack */ -#define CONFIG_SPL_STACK_SIZE 0x100 - -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_INIT_RAM_ADDR - \ - CONFIG_SYS_MALLOC_F_LEN - \ - CONFIG_SPL_STACK_SIZE) - -#endif /* __CONFIG_H */ + +#include + +#define CONFIG_CMD_SF_TEST diff --git a/include/configs/platform-auto.h b/include/configs/platform-auto.h new file mode 100644 index 0000000..475316b --- /dev/null +++ b/include/configs/platform-auto.h @@ -0,0 +1,170 @@ +/* + * This file is auto-generated by PetaLinux SDK + * DO NOT MODIFY this file, the modification will not persist + */ + +#ifndef __PLNX_CONFIG_H +#define __PLNX_CONFIG_H + +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE {115200} + +/* use serial multi for all serial devices */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +/* Board name */ +#define XILINX_BOARD_NAME ESA11 +#define CONFIG_HOSTNAME XILINX_BOARD_NAME + +/* processor - microblaze_0 */ +#define XILINX_USE_MSR_INSTR 1 +#define XILINX_FSL_LINKS 0 +#define XILINX_USE_ICACHE 1 +#define XILINX_USE_DCACHE 1 +#define XILINX_DCACHE_BYTE_SIZE 16384 +#define XILINX_PVR 2 +#define MICROBLAZE_V5 +#define CONFIG_CMD_IRQ +#define CONFIG_DCACHE +#define CONFIG_ICACHE + +/* main_memory - ddr3_sdram */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 + +/* Memory testing handling */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */ + +/* global pointer options */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* Size of malloc() pool */ +#define SIZE 0x100000 +#define CONFIG_SYS_MALLOC_LEN SIZE +#define CONFIG_SYS_MONITOR_LEN SIZE +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE) +#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_MALLOC_F_LEN 0x1000 + +/* stack */ +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_TEXT_BASE + +/* No of_control support yet*/ + +/* uart - rs232_uart */ +# define CONFIG_XILINX_UARTLITE +# define XILINX_UARTLITE_BASEADDR 0x40600000 +# define CONFIG_BAUDRATE 115200 +# define CONSOLE_ARG "console=console=ttyUL0,115200\0" + + + +/* spi_flash - spi_flash */ +#define XILINX_SPI_FLASH_BASEADDR 0x44A00000 +#define XILINX_SPI_FLASH_HIGHADDR 0x44A0FFFF +#define XILINX_SPI_FLASH_SCK_RATIO 4 +#define CONFIG_XILINX_SPI +#define XILINX_SPI_FLASH_MAX_FREQ (XILINX_SPI_FLASH_ACLK / XILINX_SPI_FLASH_SCK_RATIO) +#define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR +#define CONFIG_ENV_SPI_MAX_HZ XILINX_SPI_FLASH_MAX_FREQ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_WINBOND +#define XILINX_SPI_FLASH_ACLK 100000000 +#define XILINX_SPI_FLASH_CS 0 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0xa60000 +#define CONFIG_ENV_SIZE 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x20000 + +/* timer - axi_timer_0 */ +#define CONFIG_SYS_TIMER_0_ADDR 0x41C00000 +#define CONFIG_SYS_TIMER_0 1 +#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) +#define CONFIG_SYS_TIMER_0_IRQ 0 +#define FREQUENCE 100000000 +#define XILINX_CLOCK_FREQ 100000000 + + +/* intc - microblaze_0_axi_intc */ +#define CONFIG_SYS_INTC_0_ADDR 0x41200000 +#define CONFIG_SYS_INTC_0_NUM 3 +#define CONFIG_SYS_INTC_0 1 + +/* FPGA */ + +/* BOOTP options */ +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/*Command line configuration.*/ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_SAVES + +/* Miscellaneous configurable options */ +//#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 2048/* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_LONGHELP + +/* architecture dependent code */ +#define CONFIG_SYS_USR_EXCEP /* user exception */ +#define CONFIG_SYS_HZ 1000 + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Make the BOOTM LEN big enough for the compressed image */ +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +/* auto-boot delay */ +#define CONFIG_BOOTDELAY 4 + +/* Don't define BOOTARGS, we get it from the DTB chosen fragment */ +#undef CONFIG_BOOTARGS + +#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */ + +/* FIT image support */ +#define CONFIG_FIT 1 +#define CONFIG_LMB +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ + +/* Initial memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ 0x8000000 + +/* PREBOOT */ +#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot; echo; dhcp" + +/* Extra U-Boot Env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ + "nor0=flash-0\0"\ + "mtdparts=mtdparts=flash-0:"\ + "256k(u-boot),256k(env),3m(kernel),"\ + "1m(romfs),1m(cramfs),-(jffs2)\0"\ + "nc=setenv stdout nc;"\ + "setenv stdin nc\0" \ + "serial=setenv stdout serial;"\ + "setenv stdin serial\0"\ + "ethaddr=00:0A:35:02:C7:19\0" + +/* BOOTCOMMAND */ +#define CONFIG_BOOTCOMMAND "run default_bootcmd" + +#undef CONFIG_SPL_BUILD /* Disable SPL by default*/ + +#endif /* __PLNX_CONFIG_H */