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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id g99sm21730918wrd.72.2017.11.21.04.01.10 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 21 Nov 2017 04:01:10 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de Date: Tue, 21 Nov 2017 13:00:55 +0100 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Subject: [U-Boot] [PATCH v2 02/11] arm64: zynqmp: mp: Correct the R5 release sequence X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Siva Durga Prasad Paladugu This patch corrects the R5 release sequence by adding the below steps. 1. Flush dcache to ensure that image loaded into memory. 2. Keep R5 reset just to ensure R5 in reset. 3. Disable caches before accessing TCM as with out this A53 can do speculative and may result in ECC failures if TCM's are not initialized. So, it is always better to disable dcaches before accessing TCM and enable back. Signed-off-by: Siva Durga Prasad Paladugu Reported-by: John Linn Signed-off-by: Michal Simek --- Changes in v2: None arch/arm/cpu/armv8/zynqmp/mp.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c index 76f889ba7d9e..3ea24b47630c 100644 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -257,22 +257,36 @@ int cpu_release(int nr, int argc, char * const argv[]) boot_addr = ZYNQMP_R5_LOVEC_ADDR; } + /* + * Since we don't know where the user may have loaded the image + * for an R5 we have to flush all the data cache to ensure + * the R5 sees it. + */ + flush_dcache_all(); + if (!strncmp(argv[1], "lockstep", 8)) { printf("R5 lockstep mode\n"); + set_r5_reset(LOCK); set_r5_tcm_mode(LOCK); set_r5_halt_mode(HALT, LOCK); set_r5_start(boot_addr); enable_clock_r5(); release_r5_reset(LOCK); + dcache_disable(); write_tcm_boot_trampoline(boot_addr_uniq); + dcache_enable(); set_r5_halt_mode(RELEASE, LOCK); } else if (!strncmp(argv[1], "split", 5)) { printf("R5 split mode\n"); + set_r5_reset(SPLIT); set_r5_tcm_mode(SPLIT); set_r5_halt_mode(HALT, SPLIT); + set_r5_start(boot_addr); enable_clock_r5(); release_r5_reset(SPLIT); + dcache_disable(); write_tcm_boot_trampoline(boot_addr_uniq); + dcache_enable(); set_r5_halt_mode(RELEASE, SPLIT); } else { printf("Unsupported mode\n");