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[v2,04/17] board: cssi: Initialise port F on MIAE

Message ID ac5d1185416029f918d28ed71ea6a9d22555a8cd.1713160866.git.christophe.leroy@csgroup.eu
State Accepted
Commit 8ec8fd6983b499faa29b7469ac666aad93b57ec0
Delegated to: Tom Rini
Headers show
Series Misc changes for CSSI boards | expand

Commit Message

Christophe Leroy April 15, 2024, 6:07 a.m. UTC 
From: Hugo Dubois <hugo.dubois.ext@csgroup.eu>

When equipped with the SRSA audio board, MIAE equipment
has an additional port called port F.

Initialise that port just like other ports of the board, so
that it is already configured when starting Linux kernel.

Signed-off-by: Hugo Dubois <hugo.dubois.ext@csgroup.eu>
Reviewed-by: CASAUBON Jean Michel <jean-michel.casaubon@csgroup.eu>
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
 board/cssi/common/common.c | 36 ++++++++++++++++++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)
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Patch

diff --git a/board/cssi/common/common.c b/board/cssi/common/common.c
index 7ecf772620..6848efd43b 100644
--- a/board/cssi/common/common.c
+++ b/board/cssi/common/common.c
@@ -208,12 +208,44 @@  void misc_init_r_common(void)
 	}
 }
 
+static void iop_setup_fpgam_common(void)
+{
+	u8 far_id = in_8(ADDR_FPGA_R_BASE + 0x43) >> 5;
+
+	if (far_id == FAR_CASRSA) {
+		/*
+		 * PFDIR[15]  = 0 [0x01]
+		 * PFDIR[14]  = 1 [0x02]
+		 * PFDIR[13]  = 1 [0x04]
+		 */
+		clrsetbits_8(ADDR_FPGA_R_BASE + 0x37, 0x01, 0x06);
+		/*
+		 * PFODR[15]  = 1 [0x01]
+		 * PFODR[14]  = 0 [0x02]
+		 * PFODR[13]  = 0 [0x04]
+		 */
+		clrsetbits_8(ADDR_FPGA_R_BASE + 0x39, 0x06, 0x01);
+		/*
+		 * PFDAT[15]  = 0 [0x01]
+		 * PFDAT[14]  = 1 [0x02]
+		 * PFDAT[13]  = 1 [0x04]
+		 * PFDAT[12]  = 1 [0x08]
+		 */
+		clrsetbits_8(ADDR_FPGA_R_BASE + 0x3B, 0x01, 0x0E);
+
+		/* Setup TOR_OUT */
+		out_8(ADDR_FPGA_R_BASE + 0x32, 0x2A);
+	}
+}
+
 void iop_setup_common(void)
 {
 	u8 type = in_8(ADDR_FPGA_R_BASE);
 
-	if (type == TYPE_MCR)
+	if (type == TYPE_MCR) {
 		iop_setup_mcr();
-	else if (type == TYPE_MIAE)
+	} else if (type == TYPE_MIAE) {
 		iop_setup_miae();
+		iop_setup_fpgam_common();
+	}
 }