Message ID | a5508d5de04965e27fe07a7d65388a5659fbab9e.1603024480.git.baruch@tkos.co.il |
---|---|
State | Superseded |
Delegated to: | Stefan Roese |
Headers | show |
Series | mtd: pxa3xx_nand: add support for Armada 8k | expand |
On 18.10.20 14:56, Baruch Siach wrote: > From: Shmuel Hazan <shmuel.h@siklu.com> > > Align node properties to kernel dts node. > > Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility > with the current driver. > > Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com> > Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Thanks, Stefan > --- > arch/arm/dts/armada-cp110-slave.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi > index b426a4eb6910..6cf217783709 100644 > --- a/arch/arm/dts/armada-cp110-slave.dtsi > +++ b/arch/arm/dts/armada-cp110-slave.dtsi > @@ -267,6 +267,22 @@ > utmi-port = <UTMI_PHY_TO_USB3_HOST0>; > status = "disabled"; > }; > + > + cps_nand: nand@720000 { > + compatible = "marvell,armada-8k-nand-controller", > + "marvell,armada370-nand-controller"; > + reg = <0x720000 0x54>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "core", "reg"; > + clocks = <&cps_syscon0 1 2>, > + <&cps_syscon0 1 17>; > + marvell,system-controller = <&cps_syscon0>; > + nand-enable-arbiter; > + num-cs = <1>; > + status = "disabled"; > + }; > }; > > cps_pcie0: pcie@f4600000 { > Viele Grüße, Stefan
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi index b426a4eb6910..6cf217783709 100644 --- a/arch/arm/dts/armada-cp110-slave.dtsi +++ b/arch/arm/dts/armada-cp110-slave.dtsi @@ -267,6 +267,22 @@ utmi-port = <UTMI_PHY_TO_USB3_HOST0>; status = "disabled"; }; + + cps_nand: nand@720000 { + compatible = "marvell,armada-8k-nand-controller", + "marvell,armada370-nand-controller"; + reg = <0x720000 0x54>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "core", "reg"; + clocks = <&cps_syscon0 1 2>, + <&cps_syscon0 1 17>; + marvell,system-controller = <&cps_syscon0>; + nand-enable-arbiter; + num-cs = <1>; + status = "disabled"; + }; }; cps_pcie0: pcie@f4600000 {