| Message ID | VI1P190MB0381AF5DB7D0D2D74F820F40FB580@VI1P190MB0381.EURP190.PROD.OUTLOOK.COM |
|---|---|
| State | Changes Requested |
| Delegated to: | Daniel Schwierzeck |
| Headers | show |
| Series | mips: dts: Fix PIC32MZDA GPIO register definitions and dtc warnings | expand |
Am Samstag, den 22.08.2020, 16:36 +0000 schrieb John Robertson: > Currently GPIO operations (e.g. gpio status -a) don't work at all. > > Signed-off-by: John Robertson <john.robertson@simiatec.com> > --- > > arch/mips/dts/pic32mzda.dtsi | 58 +++++++++++++++++++++--------------- > 1 file changed, 34 insertions(+), 24 deletions(-) > > diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi > index 4c8b7a9a0b..71864d3fff 100644 > --- a/arch/mips/dts/pic32mzda.dtsi > +++ b/arch/mips/dts/pic32mzda.dtsi > @@ -26,8 +26,13 @@ > }; > > cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > cpu@0 { > compatible = "mips,mips14kc"; > + device-type = "cpu"; > + reg = <0>; > }; > }; > > @@ -40,6 +45,7 @@ > uart1: serial@1f822000 { > compatible = "microchip,pic32mzda-uart"; > reg = <0x1f822000 0x50>; > + interrupt-parent = <&evic>; I guess that fixes the DTC warnings. Can you split this into a separate commit? > interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; > status = "disabled"; > clocks = <&clock PB2CLK>; > @@ -48,6 +54,7 @@ > uart2: serial@1f822200 { > compatible = "microchip,pic32mzda-uart"; > reg = <0x1f822200 0x50>; > + interrupt-parent = <&evic>; > interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&clock PB2CLK>; > status = "disabled"; > @@ -56,6 +63,7 @@ > uart6: serial@1f822a00 { > compatible = "microchip,pic32mzda-uart"; > reg = <0x1f822a00 0x50>; > + interrupt-parent = <&evic>; > interrupts = <188 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&clock PB2CLK>; > status = "disabled"; > @@ -69,6 +77,8 @@ > }; > > pinctrl: pinctrl@1f801400 { > + #address-cells = <1>; > + #size-cells = <1>; > compatible = "microchip,pic32mzda-pinctrl"; > reg = <0x1f801400 0x100>, /* in */ > <0x1f801500 0x200>, /* out */ > @@ -76,75 +86,72 @@ > reg-names = "ppsin","ppsout","port"; > status = "disabled"; > > - ranges = <0 0x1f860000 0xa00>; > - #address-cells = <1>; > - #size-cells = <1>; > - gpioA: gpio0@0 { > + gpioA: gpio0@1f860000 { > compatible = "microchip,pic32mzda-gpio"; > - reg = <0x000 0x48>; > + reg = <0x1f860000 0xe0>; I guess that's rather a regression or change in DM address translation or maybe the GPIO driver misses some updates for DM core API. Changing the device-tree is the wrong approach. > gpio-controller; > #gpio-cells = <2>; > }; > > - gpioB: gpio1@100 { > + gpioB: gpio1@1f860100 { > compatible = "microchip,pic32mzda-gpio"; > - reg = <0x100 0x48>; > + reg = <0x1f860100 0xe0>; > gpio-controller; > #gpio-cells = <2>; > }; > > - gpioC: gpio2@200 { > + gpioC: gpio2@1f860200 { > compatible = "microchip,pic32mzda-gpio"; > - reg = <0x200 0x48>; > + reg = <0x1f860200 0xe0>; > gpio-controller; > #gpio-cells = <2>; > }; > > - gpioD: gpio3@300 { > + gpioD: gpio3@1f860300 { > compatible = "microchip,pic32mzda-gpio"; > - reg = <0x300 0x48>; > + reg = <0x1f860300 0xe0>; > gpio-controller; > #gpio-cells = <2>; > }; > > - gpioE: gpio4@400 { > + gpioE: gpio4@1f860400 { > compatible = "microchip,pic32mzda-gpio"; > - reg = <0x400 0x48>; > + reg = <0x1f860400 0xe0>; > gpio-controller; > #gpio-cells = <2>; > }; > > - gpioF: gpio5@500 { > + gpioF: gpio5@1f860500 { > compatible = "microchip,pic32mzda-gpio"; > - reg = <0x500 0x48>; > + reg = <0x1f860500 0xe0>; > gpio-controller; > #gpio-cells = <2>; > }; > > - gpioG: gpio6@600 { > + gpioG: gpio6@1f860600 { > compatible = "microchip,pic32mzda-gpio"; > - reg = <0x600 0x48>; > + reg = <0x1f860600 0xe0>; > gpio-controller; > #gpio-cells = <2>; > }; > > - gpioH: gpio7@700 { > + gpioH: gpio7@1f860700 { > compatible = "microchip,pic32mzda-gpio"; > - reg = <0x700 0x48>; > + reg = <0x1f860700 0xe0>; > gpio-controller; > #gpio-cells = <2>; > }; > > - gpioJ: gpio8@800 { > + gpioJ: gpio9@1f860800 { > compatible = "microchip,pic32mzda-gpio"; > - reg = <0x800 0x48>; > + reg = <0x1f860800 0xe0>; > gpio-controller; > #gpio-cells = <2>; > }; > > - gpioK: gpio9@900 { > + gpioK: gpio10@1f860900 { > compatible = "microchip,pic32mzda-gpio"; > - reg = <0x900 0x48>; > + reg = <0x1f860900 0xe0>; > gpio-controller; > #gpio-cells = <2>; > }; > @@ -153,6 +160,7 @@ > sdhci: sdhci@1f8ec000 { > compatible = "microchip,pic32mzda-sdhci"; > reg = <0x1f8ec000 0x100>; > + interrupt-parent = <&evic>; > interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&clock REF4CLK>, <&clock PB5CLK>; > clock-names = "base_clk", "sys_clk"; > @@ -164,6 +172,7 @@ > ethernet: ethernet@1f882000 { > compatible = "microchip,pic32mzda-eth"; > reg = <0x1f882000 0x1000>; > + interrupt-parent = <&evic>; > interrupts = <153 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&clock PB5CLK>; > status = "disabled"; > @@ -176,6 +185,7 @@ > reg = <0x1f8e3000 0x1000>, > <0x1f884000 0x1000>; > reg-names = "mc", "control"; > + interrupt-parent = <&evic>; > interrupts = <132 IRQ_TYPE_EDGE_RISING>, > <133 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&clock PB5CLK>;
diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi index 4c8b7a9a0b..71864d3fff 100644 --- a/arch/mips/dts/pic32mzda.dtsi +++ b/arch/mips/dts/pic32mzda.dtsi @@ -26,8 +26,13 @@ }; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "mips,mips14kc"; + device-type = "cpu"; + reg = <0>; }; }; @@ -40,6 +45,7 @@ uart1: serial@1f822000 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822000 0x50>; + interrupt-parent = <&evic>; interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; clocks = <&clock PB2CLK>; @@ -48,6 +54,7 @@ uart2: serial@1f822200 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822200 0x50>; + interrupt-parent = <&evic>; interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock PB2CLK>; status = "disabled"; @@ -56,6 +63,7 @@ uart6: serial@1f822a00 { compatible = "microchip,pic32mzda-uart"; reg = <0x1f822a00 0x50>; + interrupt-parent = <&evic>; interrupts = <188 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock PB2CLK>; status = "disabled"; @@ -69,6 +77,8 @@ }; pinctrl: pinctrl@1f801400 { + #address-cells = <1>; + #size-cells = <1>; compatible = "microchip,pic32mzda-pinctrl"; reg = <0x1f801400 0x100>, /* in */ <0x1f801500 0x200>, /* out */ @@ -76,75 +86,72 @@ reg-names = "ppsin","ppsout","port"; status = "disabled"; - ranges = <0 0x1f860000 0xa00>; - #address-cells = <1>; - #size-cells = <1>; - gpioA: gpio0@0 { + gpioA: gpio0@1f860000 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x000 0x48>; + reg = <0x1f860000 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioB: gpio1@100 { + gpioB: gpio1@1f860100 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x100 0x48>; + reg = <0x1f860100 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioC: gpio2@200 { + gpioC: gpio2@1f860200 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x200 0x48>; + reg = <0x1f860200 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioD: gpio3@300 { + gpioD: gpio3@1f860300 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x300 0x48>; + reg = <0x1f860300 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioE: gpio4@400 { + gpioE: gpio4@1f860400 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x400 0x48>; + reg = <0x1f860400 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioF: gpio5@500 { + gpioF: gpio5@1f860500 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x500 0x48>; + reg = <0x1f860500 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioG: gpio6@600 { + gpioG: gpio6@1f860600 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x600 0x48>; + reg = <0x1f860600 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioH: gpio7@700 { + gpioH: gpio7@1f860700 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x700 0x48>; + reg = <0x1f860700 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioJ: gpio8@800 { + gpioJ: gpio9@1f860800 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x800 0x48>; + reg = <0x1f860800 0xe0>; gpio-controller; #gpio-cells = <2>; }; - gpioK: gpio9@900 { + gpioK: gpio10@1f860900 { compatible = "microchip,pic32mzda-gpio"; - reg = <0x900 0x48>; + reg = <0x1f860900 0xe0>; gpio-controller; #gpio-cells = <2>; }; @@ -153,6 +160,7 @@ sdhci: sdhci@1f8ec000 { compatible = "microchip,pic32mzda-sdhci"; reg = <0x1f8ec000 0x100>; + interrupt-parent = <&evic>; interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock REF4CLK>, <&clock PB5CLK>; clock-names = "base_clk", "sys_clk"; @@ -164,6 +172,7 @@ ethernet: ethernet@1f882000 { compatible = "microchip,pic32mzda-eth"; reg = <0x1f882000 0x1000>; + interrupt-parent = <&evic>; interrupts = <153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock PB5CLK>; status = "disabled"; @@ -176,6 +185,7 @@ reg = <0x1f8e3000 0x1000>, <0x1f884000 0x1000>; reg-names = "mc", "control"; + interrupt-parent = <&evic>; interrupts = <132 IRQ_TYPE_EDGE_RISING>, <133 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock PB5CLK>;
Currently GPIO operations (e.g. gpio status -a) don't work at all. Signed-off-by: John Robertson <john.robertson@simiatec.com> --- arch/mips/dts/pic32mzda.dtsi | 58 +++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 24 deletions(-)