From patchwork Mon Nov 18 22:54:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 292225 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6CD0C2C009D for ; Tue, 19 Nov 2013 09:54:43 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3752A4B301; Mon, 18 Nov 2013 23:54:40 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PmvxxfciIQha; Mon, 18 Nov 2013 23:54:40 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2DA794B22A; Mon, 18 Nov 2013 23:54:38 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BBD0D4B22A for ; Mon, 18 Nov 2013 23:54:29 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cRR9loTB-Ugo for ; Mon, 18 Nov 2013 23:54:24 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-we0-f172.google.com (mail-we0-f172.google.com [74.125.82.172]) by theia.denx.de (Postfix) with ESMTPS id 68C024B229 for ; Mon, 18 Nov 2013 23:54:17 +0100 (CET) Received: by mail-we0-f172.google.com with SMTP id t60so1961706wes.31 for ; Mon, 18 Nov 2013 14:54:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=190Ig7AxcQKk8YCwtCGHnfdzxqhqHDGMTXICtA7I/Ns=; b=biX74k5HPmMYFffs254laSkZv0YKLl+VzqBq7Gc5bfkrh0bgXcFu+qxtYVJ4RKeEdE bxwY4G0p04tL+vXR7aHM/uBq5K/R4Eit96+ky5bDyV9OEvxzQpcE0clgK0M4rQUfsize Egik7xcowQXta/cZcKxyNnLCmKNg1XGSJexltpcGSilKkypLFHrsonUf/EptOiHo+JEs sAFI4dF4RSTLPofZDgxFv/zmGZ9V66VbQoGdDbo3dKWc0zjSRDuLS+qwPkAlf3ekob1Y Y7vIXtAbvyNayWg8StkVZMWlxhNa+PZT+Q5N8fHAx8PeODzPiqKtQCTsNGsc0HpkG+EG Fkmw== X-Gm-Message-State: ALoCoQnCVZxNdo17e6HSL51CcruTJC1SMNVNenpKavUBN3/oYLpChThyatRX7czxDmMF4xQrl4m6 MIME-Version: 1.0 X-Received: by 10.180.208.4 with SMTP id ma4mr9368201wic.43.1384815254419; Mon, 18 Nov 2013 14:54:14 -0800 (PST) Received: by 10.216.151.201 with HTTP; Mon, 18 Nov 2013 14:54:14 -0800 (PST) In-Reply-To: References: <20131118140621.GA3942@panicking> <20131118153746.GB420@bill-the-cat> <20131118160600.GD420@bill-the-cat> Date: Mon, 18 Nov 2013 23:54:14 +0100 Message-ID: From: Michael Trimarchi To: Tom Rini Cc: "u-boot@lists.denx.de" Subject: Re: [U-Boot] [PATCH] arm: omap3: Add uart4 omap3 adddress X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Hi On Mon, Nov 18, 2013 at 5:09 PM, Michael Trimarchi wrote: > Hi Tom > > On Mon, Nov 18, 2013 at 5:06 PM, Tom Rini wrote: >> On Mon, Nov 18, 2013 at 04:58:33PM +0100, Michael Trimarchi wrote: >>> Hi Tom >>> >>> On Mon, Nov 18, 2013 at 4:37 PM, Tom Rini wrote: >>> > On Mon, Nov 18, 2013 at 03:06:21PM +0100, Michael Trimarchi wrote: >>> >> This patch add the OMAP34XX_UART4 memory address >>> >> >>> >> Signed-off-by: Michael Trimarchi >>> >> --- >>> >> arch/arm/include/asm/arch-omap3/omap3.h | 1 + >>> >> 1 file changed, 1 insertion(+) >>> >> >>> >> diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h >>> >> index 7fb549a..65a5995 100644 >>> >> --- a/arch/arm/include/asm/arch-omap3/omap3.h >>> >> +++ b/arch/arm/include/asm/arch-omap3/omap3.h >>> >> @@ -55,6 +55,7 @@ struct control_prog_io { >>> >> #define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) >>> >> #define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) >>> >> #define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) >>> >> +#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000) >>> >> >>> >> /* General Purpose Timers */ >>> >> #define OMAP34XX_GPT1 0x48318000 >>> > >>> > What needs this? Thanks! >>> >>> I have a board the use uart4 as a console. I'm working to have it as an option >>> in omap3 code. >> >> Are you going to post the board? > > The product name is Morrison and I'm working on it. We are on pcb > design and I'm working > on the first sample trying to fix some problems. It is based on DM47xx > cpu and I don't know if > I will post the patches soon on it. This patch doesn't introduce any regression > right now > This is an idea of what can be the uart clock enable for uart4. >> >> -- >> Tom Michael diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 1bc27bd..1ff54db 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -677,16 +677,24 @@ void per_clocks_enable(void) sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */ sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */ -#ifdef CONFIG_SYS_NS16550 +#ifdef CONFIG_SYS_NS16550_COM1 /* Enable UART1 clocks */ sr32(&prcm_base->fclken1_core, 13, 1, 0x1); sr32(&prcm_base->iclken1_core, 13, 1, 0x1); +#endif +#ifdef CONFIG_SYS_NS16550_COM3 /* UART 3 Clocks */ sr32(&prcm_base->fclken_per, 11, 1, 0x1); sr32(&prcm_base->iclken_per, 11, 1, 0x1); #endif +#ifdef CONFIG_SYS_NS16550_COM4 + /* UART 4 Clocks */ + sr32(&prcm_base->fclken_per, 18, 1, 0x1); + sr32(&prcm_base->iclken_per, 18, 1, 0x1); +#endif + #ifdef CONFIG_OMAP3_GPIO_2 sr32(&prcm_base->fclken_per, 13, 1, 1); sr32(&prcm_base->iclken_per, 13, 1, 1);