From patchwork Wed Nov 18 11:30:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 545961 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0AA7514145C for ; Wed, 18 Nov 2015 22:30:30 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=Kb4Qw8KV; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7AB084B76A; Wed, 18 Nov 2015 12:30:26 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LiPyjphIkTll; Wed, 18 Nov 2015 12:30:26 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B73F14B74D; Wed, 18 Nov 2015 12:30:25 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E5304B74D for ; Wed, 18 Nov 2015 12:30:23 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hUg7YZE25i-u for ; Wed, 18 Nov 2015 12:30:23 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ig0-f173.google.com (mail-ig0-f173.google.com [209.85.213.173]) by theia.denx.de (Postfix) with ESMTPS id 147D54B748 for ; Wed, 18 Nov 2015 12:30:19 +0100 (CET) Received: by igbxm8 with SMTP id xm8so35980303igb.1 for ; Wed, 18 Nov 2015 03:30:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=6AhjYgsMRAv+NfdsPbc0QVSZ76XMYIJOgfUgs5wgAIs=; b=Kb4Qw8KV6JL2y3LO1tAxe9SYBZ1GcwX0HTnRacKVuicHeDNUFAYvrVCYQh8oBxVMFA WLXSZldwIgE1brTwQ0HsHE9aW4cd5T6akLkFn+mVulchYYxE2J1ZHhLdNF8tnP2fBK7K weuK1ngU/IhFHAf1loK15EZ+wlBmixXudKfFjLUa+XBqhz666fZiWf2n1US2k8AOcJhz ew6rVBjfGQDvNrusEkmGQLyYoUHvRZhHUFnl6SBsqljdCQrIsrA7S/pGacIWyS14WuUX gLwjD1y0WJXfjZyATWWfF6d2Wtl8dSglxAfP6VSJTVN953RqCqpeULG9COY4ELSkW5lZ 4l0A== MIME-Version: 1.0 X-Received: by 10.50.13.42 with SMTP id e10mr6653366igc.72.1447846218352; Wed, 18 Nov 2015 03:30:18 -0800 (PST) Received: by 10.79.1.76 with HTTP; Wed, 18 Nov 2015 03:30:18 -0800 (PST) In-Reply-To: <564C128D.1040806@gmail.com> References: <1447777546-18122-1-git-send-email-fabio.estevam@freescale.com> <564C128D.1040806@gmail.com> Date: Wed, 18 Nov 2015 09:30:18 -0200 Message-ID: From: Fabio Estevam To: Stefan Roese Cc: Fabio Estevam , Joe Hershberger , U-Boot-Denx , Tom Rini Subject: Re: [U-Boot] [PATCH] Revert "net: phy: delay only if reset handler is registered" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Hi Stefan, On Wed, Nov 18, 2015 at 3:54 AM, Stefan Roese wrote: > I'm not sure if this revert is the right way to solve this problem. > Please take a look at my answer a few weeks ago: > > https://www.mail-archive.com/u-boot@lists.denx.de/msg191206.html > > As mentioned in my mail above, the delay should be added after > the deassertion of the PHY reset signal. And not here in > phy_find_by_mask() for all boards. > > I just checked the code in mx6sxsabresd.c. Here also the delay is > missing: > > /* Reset AR8031 PHY */ > gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); > udelay(500); > gpio_set_value(IMX_GPIO_NR(2, 7), 1); > > Could you please test with this change: > > /* Reset AR8031 PHY */ > gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); > udelay(500); > gpio_set_value(IMX_GPIO_NR(2, 7), 1); > + udelay(1500); > > Or even better, check how long the reset needs to be inactive > before the PHY starts to work. Sure, I have even tried: and it does not work here: U-Boot 2016.01-rc1-00022-gfe52456-dirty (Nov 18 2015 - 09:28:02 -0200) CPU: Freescale i.MX6SX rev1.0 996 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 44C Reset cause: POR Board: MX6SX SABRE SDB I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 PCI: pcie phy link never came up In: serial Out: serial Err: serial Net: Board Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Booting from net ... No ethernet found. No ethernet found. Bad Linux ARM zImage magic! Regards, Fabio Estevam --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -163,8 +163,9 @@ static int setup_fec(void) /* Reset AR8031 PHY */ gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); - udelay(500); + udelay(50000); gpio_set_value(IMX_GPIO_NR(2, 7), 1); + udelay(50000); reg = readl(&anatop->pll_enet); reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;