From patchwork Mon May 25 14:36:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 476227 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 10A531401B5 for ; Tue, 26 May 2015 00:37:37 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=gFva7N8+; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 03B8D4B7AC; Mon, 25 May 2015 16:37:25 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xgn67qU92MBl; Mon, 25 May 2015 16:37:24 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AC4244B7A4; Mon, 25 May 2015 16:37:21 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6D8C24B705 for ; Mon, 25 May 2015 16:37:12 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eCPD4BAFrDfS for ; Mon, 25 May 2015 16:37:12 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qg0-f44.google.com (mail-qg0-f44.google.com [209.85.192.44]) by theia.denx.de (Postfix) with ESMTPS id 188B04B741 for ; Mon, 25 May 2015 16:37:02 +0200 (CEST) Received: by qgew3 with SMTP id w3so45942175qge.2 for ; Mon, 25 May 2015 07:37:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:from:to:subject:date:in-reply-to:references:mime-version :content-type; bh=dHGZAGgi7y90009aaW6vP28q8br3fPGbo2Rpc+4oZVE=; b=gFva7N8+jKZMNKp9BkEGgxwFOF2vt02MGTs8OMLhByi72z29xtqGfsEYOmi50JKyf8 0qDfhryq4e6cTwuvtkUqgnwFNWP3rcxfXRP+e1ewywv9D2mpYczPUe0tquRoC+dNKzWB toVwxMR61EDvlqze9H+9GVP2lr8YeZPVvwHcns6pPOBEDOQ3iM2j1EiULIuFE9jUGPcQ WrGQE8Qyd5ObU6w1hrtez3ZbBVW5X6SVb/jRtvanDunUP6VTAELbwZRMG/oaaRBm+Q4G gIQ+53qph6lEi03LFq2R9574TV1eQMxle2MmuK6QK9JO9jyGNNXECToT3+uMCEVuLrxb b7vw== X-Received: by 10.140.27.211 with SMTP id 77mr7032076qgx.64.1432564621756; Mon, 25 May 2015 07:37:01 -0700 (PDT) Received: from mail.hotmail.com (blu004-wss1s5.hotmail.com. [134.170.2.220]) by mx.google.com with ESMTPSA id e69sm3834276qkh.19.2015.05.25.07.37.01 (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 25 May 2015 07:37:01 -0700 (PDT) Received: from BLU437-SMTP35 ([134.170.2.215]) by BLU004-WSS1S5.hotmail.com over TLS secured channel with Microsoft SMTPSVC(7.5.7601.22751); Mon, 25 May 2015 07:37:00 -0700 X-TMN: [Vvqhdk2FraQtCGOzHueDyQP64RbMmZr1] Message-ID: From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Mon, 25 May 2015 22:36:31 +0800 X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1432564591-23963-1-git-send-email-bmeng.cn@gmail.com> References: <1432564591-23963-1-git-send-email-bmeng.cn@gmail.com> X-OriginalArrivalTime: 25 May 2015 14:36:59.0967 (UTC) FILETIME=[422744F0:01D096F8] MIME-Version: 1.0 Subject: [U-Boot] [PATCH 6/6] x86: qemu: Implement PIRQ routing X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Support QEMU PIRQ routing via device tree on both i440fx and q35 platforms. With this commit, Linux booting on QEMU from U-Boot has working ATA/SATA, USB and ethernet. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/coreboot/coreboot.c | 5 +++++ arch/x86/cpu/qemu/qemu.c | 8 ++++++++ arch/x86/dts/qemu-x86_i440fx.dts | 16 ++++++++++++++++ arch/x86/dts/qemu-x86_q35.dts | 32 ++++++++++++++++++++++++++++++++ configs/qemu-x86_defconfig | 1 + include/configs/qemu-x86_i440fx.h | 1 + include/configs/qemu-x86_q35.h | 1 + 7 files changed, 64 insertions(+) diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 12b07bf..041e51e 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -78,3 +78,8 @@ int misc_init_r(void) { return 0; } + +int arch_misc_init(void) +{ + return 0; +} diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 0f98476..930d2b6 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -35,3 +36,10 @@ void reset_cpu(ulong addr) /* cold reset */ x86_full_reset(); } + +int arch_misc_init(void) +{ + pirq_init(); + + return 0; +} diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 4cf843b..557428a 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -6,6 +6,8 @@ /dts-v1/; +#include + /include/ "skeleton.dtsi" /include/ "serial.dtsi" @@ -29,6 +31,20 @@ ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + irq-router@1,0 { + reg = <0x00000800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 4>; + intel,pirq-mask = <0x0e40>; + intel,pirq-routing = < + /* PIIX UHCI */ + PCI_BDF(0, 1, 2) INTD PIRQD + /* e1000 NIC */ + PCI_BDF(0, 3, 0) INTA PIRQC + >; + }; }; }; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 6c89283..c8e1a55 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -6,6 +6,18 @@ /dts-v1/; +#include + +/* ICH9 IRQ router has discrete PIRQ control registers */ +#undef PIRQE +#undef PIRQF +#undef PIRQG +#undef PIRQH +#define PIRQE 8 +#define PIRQF 9 +#define PIRQG 10 +#define PIRQH 11 + /include/ "skeleton.dtsi" /include/ "serial.dtsi" @@ -29,6 +41,26 @@ ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0x0e40>; + intel,pirq-routing = < + /* e1000 NIC */ + PCI_BDF(0, 2, 0) INTA PIRQG + /* ICH9 UHCI */ + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 29, 1) INTB PIRQB + PCI_BDF(0, 29, 2) INTC PIRQC + /* ICH9 EHCI */ + PCI_BDF(0, 29, 7) INTD PIRQD + /* ICH9 SATA */ + PCI_BDF(0, 31, 2) INTA PIRQA + >; + }; }; }; diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index a894db6..a5251b5 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -6,3 +6,4 @@ CONFIG_OF_SEPARATE=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_111=y +CONFIG_GENERATE_PIRQ_TABLE=y diff --git a/include/configs/qemu-x86_i440fx.h b/include/configs/qemu-x86_i440fx.h index 53d917d..b710cf7 100644 --- a/include/configs/qemu-x86_i440fx.h +++ b/include/configs/qemu-x86_i440fx.h @@ -14,6 +14,7 @@ #include #define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_ARCH_MISC_INIT #define CONFIG_X86_SERIAL diff --git a/include/configs/qemu-x86_q35.h b/include/configs/qemu-x86_q35.h index ef81ad3..db26676 100644 --- a/include/configs/qemu-x86_q35.h +++ b/include/configs/qemu-x86_q35.h @@ -14,6 +14,7 @@ #include #define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_ARCH_MISC_INIT #define CONFIG_X86_SERIAL