diff mbox

[U-Boot,01/10] x86: Change pci option rom area MTRR setting to cacheable

Message ID BLU437-SMTP1880AC15AC9999A0DB69F2BF9A0@phx.gbl
State Accepted
Delegated to: Simon Glass
Headers show

Commit Message

Bin Meng July 15, 2015, 8:23 a.m. UTC 
Turn on cache on the pci option rom area to improve the performance.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/cpu.c          | 27 ++++++++++++++++++++-------
 arch/x86/include/asm/mtrr.h |  2 ++
 2 files changed, 22 insertions(+), 7 deletions(-)

Comments

Simon Glass July 18, 2015, 2:37 p.m. UTC | #1 
On 15 July 2015 at 02:23, Bin Meng <bmeng.cn@gmail.com> wrote:
> Turn on cache on the pci option rom area to improve the performance.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/cpu.c          | 27 ++++++++++++++++++++-------
>  arch/x86/include/asm/mtrr.h |  2 ++
>  2 files changed, 22 insertions(+), 7 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass July 20, 2015, 2:04 a.m. UTC | #2 
On 18 July 2015 at 08:37, Simon Glass <sjg@chromium.org> wrote:
> On 15 July 2015 at 02:23, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Turn on cache on the pci option rom area to improve the performance.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/cpu/cpu.c          | 27 ++++++++++++++++++++-------
>>  arch/x86/include/asm/mtrr.h |  2 ++
>>  2 files changed, 22 insertions(+), 7 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-x86, thanks!
diff mbox

Patch

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index af927b9..b4e0fd9 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -363,13 +363,26 @@  int x86_cpu_init_f(void)
 		mtrr_cap = native_read_msr(MTRR_CAP_MSR);
 		if (mtrr_cap & MTRR_CAP_FIX) {
 			/* Mark the VGA RAM area as uncacheable */
-			native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0);
-
-			/* Mark the PCI ROM area as uncacheable */
-			native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0);
-			native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0);
-			native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0);
-			native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0);
+			native_write_msr(MTRR_FIX_16K_A0000_MSR,
+					 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
+					 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
+
+			/*
+			 * Mark the PCI ROM area as cacheable to improve ROM
+			 * execution performance.
+			 */
+			native_write_msr(MTRR_FIX_4K_C0000_MSR,
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+			native_write_msr(MTRR_FIX_4K_C8000_MSR,
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+			native_write_msr(MTRR_FIX_4K_D0000_MSR,
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+			native_write_msr(MTRR_FIX_4K_D8000_MSR,
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
 
 			/* Enable the fixed range MTRRs */
 			msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index 70762ee..f9b30f6 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -55,6 +55,8 @@ 
 #define MTRR_FIX_4K_F0000_MSR	0x26e
 #define MTRR_FIX_4K_F8000_MSR	0x26f
 
+#define MTRR_FIX_TYPE(t)	((t << 24) | (t << 16) | (t << 8) | t)
+
 #if !defined(__ASSEMBLER__)
 
 /**