From patchwork Wed Jul 15 08:23:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 495520 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6F0681402BA for ; Wed, 15 Jul 2015 18:25:57 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=YcgmO0Mn; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0834D4B718; Wed, 15 Jul 2015 10:24:48 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PrQKsxCTXBbS; Wed, 15 Jul 2015 10:24:47 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 29C7D4B721; Wed, 15 Jul 2015 10:24:44 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 358504B67B for ; Wed, 15 Jul 2015 10:24:42 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6unf92j3xpvZ for ; Wed, 15 Jul 2015 10:24:42 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qk0-f182.google.com (mail-qk0-f182.google.com [209.85.220.182]) by theia.denx.de (Postfix) with ESMTPS id 0FC754B6BE for ; Wed, 15 Jul 2015 10:24:30 +0200 (CEST) Received: by qkbp125 with SMTP id p125so23191099qkb.2 for ; Wed, 15 Jul 2015 01:24:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:from:to:subject:date:in-reply-to:references:mime-version :content-type; bh=2LIgTzDqegx8L26HLrZn5WM/xdSkudjfk2karcFIuOU=; b=YcgmO0MnFhmME7hgY6VNJ/LxAY7t6ho99CqahQ2zFb3Urr4mE/aOBG03uYi8MTLatY qXec4P953zjXqGSybp1gNBem6FAT/6c8hpKp5DX3Un/askLyQqBcsz/zfjvV3A+8Wzd0 1x0whAvRjlm3AMRmarho3p1LbpTTaardGlyYc1961RMT20k5kZyJoJPHORLh1op3Gxe2 kEDDqXgcNZh+LEOpBXbp7rkqc68VxtUHD/W83Ig5sc02hZiJ8jnduZPFW92Y7+gneF2p lQRu59Sjm2kWwY/3d4psAM5j3ylUskGBf2QsiSVXLgyhzEWrywras5ejbA7EGtJxtu6A AAGQ== X-Received: by 10.140.94.132 with SMTP id g4mr5938893qge.63.1436948669380; Wed, 15 Jul 2015 01:24:29 -0700 (PDT) Received: from mail.hotmail.com (blu004-wss1s4.hotmail.com. [134.170.2.219]) by smtp.gmail.com with ESMTPSA id g33sm1911792qgg.4.2015.07.15.01.24.28 (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Jul 2015 01:24:28 -0700 (PDT) Received: from BLU437-SMTP18 ([134.170.2.215]) by BLU004-WSS1S4.hotmail.com over TLS secured channel with Microsoft SMTPSVC(7.5.7601.23008); Wed, 15 Jul 2015 01:24:27 -0700 X-TMN: [/+GIiH8O84vFv+IYzq693nQVCilT6D7T] Message-ID: From: Bin Meng To: Simon Glass , U-Boot Mailing List , Saket Sinha Date: Wed, 15 Jul 2015 16:23:42 +0800 X-Mailer: git-send-email 2.3.2 (Apple Git-55) In-Reply-To: <1436948627-1521-1-git-send-email-bmeng.cn@gmail.com> References: <1436948627-1521-1-git-send-email-bmeng.cn@gmail.com> X-OriginalArrivalTime: 15 Jul 2015 08:24:26.0719 (UTC) FILETIME=[A9A58EF0:01D0BED7] MIME-Version: 1.0 Subject: [U-Boot] [PATCH 05/10] x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently during writing MP table I/O interrupt assignment entry, we assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which however is not always the case on some platforms. Signed-off-by: Bin Meng --- arch/x86/include/asm/mpspec.h | 17 +++++++++++++++++ arch/x86/lib/mpspec.c | 23 ++++++++++++++++------- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index efa9231..ad8eba9 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -432,6 +432,23 @@ void mp_write_compat_address_space(struct mp_config_table *mc, int busid, u32 mptable_finalize(struct mp_config_table *mc); /** + * mp_determine_pci_dstirq() - Determine PCI device's int pin on the I/O APIC + * + * This determines a PCI device's interrupt pin number on the I/O APIC. + * + * This can be implemented by platform codes to handle specifal cases, which + * do not conform to the normal chipset/board design where PIRQ[A-H] are mapped + * directly to I/O APIC INTPIN#16-23. + * + * @bus: bus number of the pci device + * @dev: device number of the pci device + * @func: function number of the pci device + * @pirq: PIRQ number the PCI device's interrupt pin is routed to + * @return: interrupt pin number on the I/O APIC + */ +int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq); + +/** * write_mp_table() - Write MP table * * This writes MP table at a given address. diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index f16fbcb..f90567c 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -269,6 +269,12 @@ static bool check_dup_entry(struct mpc_config_intsrc *intsrc_base, return (i == entry_num) ? false : true; } +__weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) +{ + /* PIRQ[A-H] are connected to I/O APIC INTPIN#16-23 */ + return pirq + 16; +} + static int mptable_add_intsrc(struct mp_config_table *mc, int bus_isa, int apicid) { @@ -304,24 +310,27 @@ static int mptable_add_intsrc(struct mp_config_table *mc, for (i = 0; i < count; i++) { struct pirq_routing pr; + int bus, dev, func; + int dstirq; pr.bdf = fdt_addr_to_cpu(cell[0]); pr.pin = fdt_addr_to_cpu(cell[1]); pr.pirq = fdt_addr_to_cpu(cell[2]); + bus = PCI_BUS(pr.bdf); + dev = PCI_DEV(pr.bdf); + func = PCI_FUNC(pr.bdf); if (check_dup_entry(intsrc_base, intsrc_entries, - PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin)) { + bus, dev, pr.pin)) { debug("found entry for bus %d device %d INT%c, skipping\n", - PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), - 'A' + pr.pin - 1); + bus, dev, 'A' + pr.pin - 1); cell += sizeof(struct pirq_routing) / sizeof(u32); continue; } - /* PIRQ[A-H] are always connected to I/O APIC INTPIN#16-23 */ - mp_write_pci_intsrc(mc, MP_INT, PCI_BUS(pr.bdf), - PCI_DEV(pr.bdf), pr.pin, apicid, - pr.pirq + 16); + dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq); + mp_write_pci_intsrc(mc, MP_INT, bus, dev, pr.pin, + apicid, dstirq); intsrc_entries++; cell += sizeof(struct pirq_routing) / sizeof(u32); }