From patchwork Wed May 20 09:04:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 474238 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id F2CEA14010F for ; Wed, 20 May 2015 19:08:03 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=WY4ofx3m; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E9FB34B657; Wed, 20 May 2015 11:07:41 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 71Jk8gbsm4HN; Wed, 20 May 2015 11:07:36 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 725D34B622; Wed, 20 May 2015 11:07:17 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6145E4B62A for ; Wed, 20 May 2015 11:05:02 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xpLEuFpQb8Ir for ; Wed, 20 May 2015 11:04:52 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qk0-f172.google.com (mail-qk0-f172.google.com [209.85.220.172]) by theia.denx.de (Postfix) with ESMTPS id 8E67E4B622 for ; Wed, 20 May 2015 11:04:23 +0200 (CEST) Received: by qkgw4 with SMTP id w4so27307472qkg.3 for ; Wed, 20 May 2015 02:04:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:from:to:subject:date:in-reply-to:references:mime-version :content-type; bh=Z4Hu8JKHiQsPosLRfn704+KTCdUWK2VKYNxnqwOu7HU=; b=WY4ofx3mfniMpCly8MGth2vutVg/mY/dOsV2KjEgfkhWwMT0Jt+GXgdCHTQ5wYyBH8 pycGBfdGsmNzAt9kjlxwnwrHY0q7n6+bcXwBR9GfGar5eae7AHszEeRltmLODSbmR1dl NsfghgiZnoX3I3UNKAPysbgs3S0eD4vtnOsMs+cEqYGf8wO/L6g5sR/Mevc5k3zaG5LQ wP9c3IbzkT+m4kBF562q8aVsn7b5VKYSjM09GoBxkeMTRKjdxwAkHWwjbmwjEBKzEqDa TWOt2kTt7XrbQz4Zg0n7s09/XCfceLYPnTbkbAvbIOREA1mEM35coTHYSqfI742iCvgQ bOTA== X-Received: by 10.141.28.3 with SMTP id f3mr44126482qhe.37.1432112660515; Wed, 20 May 2015 02:04:20 -0700 (PDT) Received: from mail.hotmail.com (blu004-wss1s5.hotmail.com. [134.170.2.220]) by mx.google.com with ESMTPSA id f38sm10886490qkf.7.2015.05.20.02.04.19 (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 May 2015 02:04:20 -0700 (PDT) Received: from BLU436-SMTP175 ([134.170.2.215]) by BLU004-WSS1S5.hotmail.com over TLS secured channel with Microsoft SMTPSVC(7.5.7601.22751); Wed, 20 May 2015 02:04:19 -0700 X-TMN: [1oNnFWj9ZJbFnsugTFoIyw3bvUt6IN6G] Message-ID: From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Wed, 20 May 2015 17:04:05 +0800 X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1432112645-25312-1-git-send-email-bmeng.cn@gmail.com> References: <1432112645-25312-1-git-send-email-bmeng.cn@gmail.com> X-OriginalArrivalTime: 20 May 2015 09:04:18.0447 (UTC) FILETIME=[F41849F0:01D092DB] MIME-Version: 1.0 Subject: [U-Boot] [PATCH 2/2] x86: qemu: Turn on legacy segments decode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" By default the legacy segments C/D/E/F do not decode to system RAM. Turn on the decode via Programmable Attribute Map (PAM) registers so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/qemu/pci.c | 20 ++++++++++++++++++++ arch/x86/include/asm/arch-qemu/qemu.h | 6 ++++++ 2 files changed, 26 insertions(+) diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index c09bdf2..c9d5f3a 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +52,8 @@ int board_pci_post_scan(struct pci_controller *hose) ulong start; pci_dev_t bdf; struct pci_device_id graphic_card[] = { { 0x1234, 0x1111 } }; + u16 device; + int pam, i; /* * QEMU emulated graphic card shows in the PCI configuration space with @@ -67,6 +71,22 @@ int board_pci_post_scan(struct pci_controller *hose) debug("BIOS ran in %lums\n", get_timer(start)); } + /* + * i440FX and Q35 chipset have different PAM register offset, but with + * the same bitfield layout. Here we determine the offset based on its + * PCI device ID. + */ + device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); + pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM; + + /* + * Initialize Programmable Attribute Map (PAM) Registers + * + * Configure legacy segments C/D/E/F to system RAM + */ + for (i = 0; i < PAM_NUM; i++) + x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); + return ret; } diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h index 8d7e986..7a9901d 100644 --- a/arch/x86/include/asm/arch-qemu/qemu.h +++ b/arch/x86/include/asm/arch-qemu/qemu.h @@ -7,6 +7,12 @@ #ifndef _ARCH_QEMU_H_ #define _ARCH_QEMU_H_ +/* Programmable Attribute Map (PAM) Registers */ +#define I440FX_PAM 0x59 +#define Q35_PAM 0x90 +#define PAM_NUM 7 +#define PAM_RW 0x33 + /* I/O Ports */ #define CMOS_ADDR_PORT 0x70 #define CMOS_DATA_PORT 0x71