diff mbox

[U-Boot,v2,06/11] x86: queensbay: Change CPU_ADDR_BITS to 32

Message ID BLU436-SMTP1338D1BBB4D424C404547FBF930@phx.gbl
State Accepted
Delegated to: Simon Glass
Headers show

Commit Message

Bin Meng July 6, 2015, 8:31 a.m. UTC 
Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/queensbay/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Simon Glass July 7, 2015, 10:54 p.m. UTC | #1 
On 6 July 2015 at 02:31, Bin Meng <bmeng.cn@gmail.com> wrote:
> Per CPUID:80000008h result, the maximum physical address bits of
> TunnelCreek processor is 32 instead of default 36. This will fix
> the incorrect decoding of MTRR range mask.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/queensbay/Kconfig | 4 ++++
>  1 file changed, 4 insertions(+)

Applied to u-boot-x86, thanks!
diff mbox

Patch

diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 397e599..fbf85f2 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -38,4 +38,8 @@  config CMC_ADDR
 	  The default base address of 0xfffb0000 indicates that the binary must
 	  be located at offset 0xb0000 from the beginning of a 1MB flash device.
 
+config CPU_ADDR_BITS
+	int
+	default 32
+
 endif