From patchwork Tue Mar 15 05:39:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumar Gala X-Patchwork-Id: 86882 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C68E0B6FEB for ; Tue, 15 Mar 2011 16:59:57 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BA81E2807B; Tue, 15 Mar 2011 06:59:55 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id C8m2zO+siXwZ; Tue, 15 Mar 2011 06:59:55 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ADED428087; Tue, 15 Mar 2011 06:59:53 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8B96828087 for ; Tue, 15 Mar 2011 06:59:51 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id osTwN5w76QCP for ; Tue, 15 Mar 2011 06:59:49 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by theia.denx.de (Postfix) with ESMTPS id 5C5AC2807B for ; Tue, 15 Mar 2011 06:59:46 +0100 (CET) Received: from [IPv6:::1] (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id p2F5dHpF006371; Tue, 15 Mar 2011 00:39:18 -0500 Mime-Version: 1.0 (Apple Message framework v1082) From: Kumar Gala In-Reply-To: <20110314163735.165fd1d5@schlenkerla> Date: Tue, 15 Mar 2011 00:39:17 -0500 Message-Id: <977C59AE-9AB2-4B92-B508-C057CB172F0C@kernel.crashing.org> References: <6EC57A52-1C75-4F1A-8A43-90A06BB6D11B@kernel.crashing.org> <20110314130917.718704bf@schlenkerla> <67FE1774-18F0-4EC6-B4C0-51A0A7A7FAE2@kernel.crashing.org> <20110314163735.165fd1d5@schlenkerla> To: Scott Wood X-Mailer: Apple Mail (2.1082) Cc: Jimi Xenidis , u-boot@lists.denx.de Subject: Re: [U-Boot] p4080ds starts OS with MSR[EE]=1 and DEC armed? X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On Mar 14, 2011, at 4:37 PM, Scott Wood wrote: > On Mon, 14 Mar 2011 16:25:54 -0500 > Kumar Gala wrote: > >> >> On Mar 14, 2011, at 1:09 PM, Scott Wood wrote: >> >>> On Sat, 12 Mar 2011 16:56:09 -0600 >>> Kumar Gala wrote: >>> >>>> >>>> On Mar 3, 2011, at 8:59 AM, Jimi Xenidis wrote: >>>> >>>>> I was surprised to find myself at the decrement interrupt when running my new stuff. >>>>> That is against ePAPR, right? >>>>> Does u-boot at least make sure that the DEC is set to some large value before it leaps at me? >>>>> I don't mind forcing EE=0 but I'd like to make sure I make it that far into the code :) >>>>> -JX >>>> >>>> Jimi, >>>> >>>> Not sure how or why you are seeing this, but u-boot should disable interrupts in common/cmd_bootm.c >>>> >>>> Look for disable_interrupts() -> this should set MSR[EE] = 0. >>> >>> What about the rest of MSR -- ME/CE/DE? >> >> I dont think we ever turn on CE in u-boot, DE would only get set in some weird external debugger build. > > From arch/powerpc/cpu/mpc85xx/start.S: > > /* switch back to AS = 0 */ > lis r3,(MSR_CE|MSR_ME|MSR_DE)@h > ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l > mtmsr r3 > isync > > bl cpu_init_f > bl board_init_f > isync > > -Scott commit 15fba3279b56333bdb65ead366f82c945ed320d1 Author: Kumar Gala Date: Fri Sep 11 15:28:41 2009 -0500 ppc/85xx: Disable all async interrupt sources when we boot We should make sure to clear MSR[ME, CE, DE] when we boot an OS image since we have changed the exception vectors and the OSes vectors might not be setup we should avoid async interrupts at all costs. Signed-off-by: Kumar Gala ----- :) - k diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 48a82ed..a6d1e99 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -364,5 +364,16 @@ extern void setup_ivors(void); void arch_preboot_os(void) { + u32 msr; + + /* + * We are changing interrupt offsets and are about to boot the OS so + * we need to make sure we disable all async interrupts. EE is already + * disabled by the time we get called. + */ + msr = mfmsr(); + msr &= ~(MSR_ME|MSR_CE|MSR_DE); + mtmsr(msr); + setup_ivors(); }