diff --git a/arch/arm/cpu/armv7/spear13xx/Makefile b/arch/arm/cpu/armv7/spear13xx/Makefile
index daeffa2..fa3c841 100644
--- a/arch/arm/cpu/armv7/spear13xx/Makefile
+++ b/arch/arm/cpu/armv7/spear13xx/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-lvl_read.o
 COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-lvl_write.o
 COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-swlvl.o
 COBJS-$(CONFIG_SOC_SPEAR1340) += spl-spear1340.o
+COBJS-$(CONFIG_SOC_SPEAR1310) += spl-spear1310.o
 endif
 
 COBJS	:= $(sort $(COBJS-y))
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-spear1310.c b/arch/arm/cpu/armv7/spear13xx/spl-spear1310.c
new file mode 100644
index 0000000..263d2e1
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-spear1310.c
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/mpmc.h>
+
+static void pll_init(void)
+{
+	struct spear1310_misc_regs *const misc_p =
+		(struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+	u32 usbphycfg;
+
+	/* Initialize PLLs */
+	writel(SPEAR1310_FREQ_1000, &misc_p->pll1_frq);
+	writel(readl(&misc_p->pll1_ctr) | SPEAR1310_PLLENABLE,
+			&misc_p->pll1_ctr);
+
+	writel(SPEAR1310_FREQ_125, &misc_p->pll2_frq);
+	writel(readl(&misc_p->pll2_ctr) | SPEAR1310_PLLENABLE,
+			&misc_p->pll2_ctr);
+
+	writel(SPEAR1310_FREQ_332, &misc_p->pll3_frq);
+	writel(readl(&misc_p->pll3_ctr) | SPEAR1310_PLLENABLE,
+			&misc_p->pll3_ctr);
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+	writel(SPEAR1310_FREQ_400, &misc_p->pll4_frq);
+#elif defined(CONFIG_SPEAR_DDRFREQ533)
+	writel(SPEAR1310_FREQ_533, &misc_p->pll4_frq);
+#else
+#error Define one of the valid DDR frequency(CONFIG_SPEAR_DDRFREQ[533/400])
+#endif
+	/* strobing required for pll4 */
+	writel(0x60A, &misc_p->pll4_ctr);
+	writel(0x60E, &misc_p->pll4_ctr);
+	writel(0x606, &misc_p->pll4_ctr);
+	writel(0x60E, &misc_p->pll4_ctr);
+
+	usbphycfg = readl(&misc_p->usbphy_gen_cfg);
+	usbphycfg &= ~(SPEAR1310_COMMON_PWDN | SPEAR1310_USBPHY_POR);
+	usbphycfg |= SPEAR1310_USBPHY_RST;
+	writel(usbphycfg, &misc_p->usbphy_gen_cfg);
+
+	while (!(readl(&misc_p->usbphy_gen_cfg) & SPEAR1310_USB_PLL_LOCK))
+		;
+	usbphycfg = readl(&misc_p->usbphy_gen_cfg);
+
+	usbphycfg |= SPEAR1310_AUTOPPD_ON_OVRCURR | \
+		     SPEAR1310_UTMI_XFER_RST0 | \
+		     SPEAR1310_UTMI_XFER_RST1 | \
+		     SPEAR1310_UTMI_XFER_RST2;
+
+	writel(usbphycfg, &misc_p->usbphy_gen_cfg);
+
+	/* wait for pll locks */
+	while (!(readl(&misc_p->pll1_ctr) & SPEAR1310_PLLLOCK))
+		;
+	while (!(readl(&misc_p->pll2_ctr) & SPEAR1310_PLLLOCK))
+		;
+	while (!(readl(&misc_p->pll3_ctr) & SPEAR1310_PLLLOCK))
+		;
+	while (!(readl(&misc_p->pll4_ctr) & SPEAR1310_PLLLOCK))
+		;
+}
+
+static void sys_init(void)
+{
+	struct spear1310_misc_regs *const misc_p =
+		(struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+	u32 sysclkctrl;
+
+	/* Set system state to SLOW */
+	sysclkctrl = readl(&misc_p->sys_clk_ctrl);
+	sysclkctrl &= ~SPEAR1310_SYS_MODE_MASK;
+	sysclkctrl |= SPEAR1310_XTAL_TIMEOUT_ENB | \
+		      SPEAR1310_PLL_TIMEOUT_ENB | \
+		      SPEAR1310_SYS_MODE_REQ_SLOW;
+	writel(sysclkctrl, &misc_p->sys_clk_ctrl);
+
+	writel(SPEAR1310_PLL_TIM, &misc_p->sys_clk_plltimer);
+	writel(SPEAR1310_OSCI_TIM, &misc_p->sys_clk_oscitimer);
+
+	/* Initialize PLLs */
+	pll_init();
+
+	/* Set system state to NORMAL */
+	sysclkctrl = readl(&misc_p->sys_clk_ctrl);
+	sysclkctrl &= ~SPEAR1310_SYS_MODE_MASK;
+	sysclkctrl |= SPEAR1310_XTAL_TIMEOUT_ENB | \
+		      SPEAR1310_PLL_TIMEOUT_ENB | \
+		      SPEAR1310_SYS_MODE_REQ_NORMAL;
+	writel(sysclkctrl, &misc_p->sys_clk_ctrl);
+
+	/* Wait for system to switch to normal mode */
+	while ((readl(&misc_p->sys_clk_ctrl) & SPEAR1310_SYS_STATE_MASK) !=
+			SPEAR1310_SYS_STATE_NORMAL)
+		;
+
+#if defined(CONFIG_C3)
+	writel(readl(&misc_p->perip1_clk_enb) | SPEAR1310_C3_CLKEN,
+			&misc_p->perip1_clk_enb);
+#endif
+}
+
+static void ddr_clock_init(void)
+{
+	struct spear1310_misc_regs *const misc_p =
+		(struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+	u32 perip_clkcfg, perip2_clkenb, perip2_swrst;
+
+	perip_clkcfg = readl(&misc_p->perip_clk_cfg);
+	perip_clkcfg |= SPEAR1310_MPMCCLKPLL4;
+	writel(perip_clkcfg, &misc_p->perip_clk_cfg);
+
+	perip2_clkenb = readl(&misc_p->perip2_clk_enb);
+	perip2_clkenb |= SPEAR1310_DDRCTRL_CLKEN | SPEAR1310_DDRCORE_CLKEN;
+	writel(perip2_clkenb, &misc_p->perip2_clk_enb);
+
+	perip2_swrst = readl(&misc_p->perip2_sw_rst);
+	perip2_swrst |= SPEAR1310_DDRCTRL_RST | SPEAR1310_DDRCORE_RST;
+	writel(perip2_swrst, &misc_p->perip2_sw_rst);
+
+	perip2_swrst = readl(&misc_p->perip2_sw_rst);
+	perip2_swrst &= ~(SPEAR1310_DDRCTRL_RST | SPEAR1310_DDRCORE_RST);
+	writel(perip2_swrst, &misc_p->perip2_sw_rst);
+}
+
+static void ddr_pad_compensation(u8 enable)
+{
+	struct spear1310_misc_regs *const misc_p =
+		(struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+	if (enable) {
+		writel(0x00000400, &misc_p->compensation_ddr_cfg);
+		writel(0x00000400, &misc_p->compensation_ddr_cfg);
+		writel(0x00000400, &misc_p->compensation_ddr_cfg);
+
+		/* wait for comzcrdy done */
+		while (!(readl(&misc_p->compensation_ddr_cfg) & 0x1))
+			;
+	} else {
+		writel(0x00000000, &misc_p->compensation_ddr_cfg);
+		writel(0x00000000, &misc_p->compensation_ddr_cfg);
+		writel(0x00000000, &misc_p->compensation_ddr_cfg);
+	}
+}
+
+void ddr_init(void)
+{
+	struct spear1310_misc_regs *const misc_p =
+		(struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+#if defined(CONFIG_DDR_ECC_ENABLE)
+	u32 mpmc_cfg;
+#endif
+
+	/* Clock related settings for DDR */
+	ddr_clock_init();
+
+#if defined(CONFIG_DDR_ECC_ENABLE)
+	/*
+	 * Following modifies write access as non-bufferable
+	 * and read to happen word by word. Without this
+	 * dependent write-read are happening out of order
+	 * resulting in Linux crash.
+	 */
+	mpmc_cfg = readl(&misc_p->mpmc_cfg);
+	mpmc_cfg |= SPEAR1310_AXI0_AWCOBUF | SPEAR1310_AXI2_AWCOBUF;
+	mpmc_cfg &= ~(SPEAR1310_AXI0_CMDTHRESH_MSK | \
+			SPEAR1310_AXI2_CMDTHRESH_MSK);
+	mpmc_cfg |= (SPEAR1310_AXI0_CMDTHRESH_1 | SPEAR1310_AXI2_CMDTHRESH_1);
+	writel(mpmc_cfg, &misc_p->mpmc_cfg);
+
+	/* enable MPMC ECC gasket for all AXI ports */
+	writel(0x0, &misc_p->mpmc_ctr_sts);
+
+	/* wait for turn-on */
+	while ((readl(&misc_p->mpmc_ctr_sts) & 0xFFF))
+		;
+#endif
+
+	/* Initialize mpmc register values */
+	spear13xx_mpmc_init((u32 *)CONFIG_SYS_MPMC_BASE, CONFIG_SPEAR_MPMCREGS);
+
+	writel(SPEAR1310_PAD_VREF | SPEAR1310_DATA_PROGB | \
+		SPEAR1310_DATA_PROGA | SPEAR1310_CLK_PROGB | \
+		SPEAR1310_CLK_PROGA | SPEAR1310_CTRL_PROGB | \
+		SPEAR1310_CTRL_PROGA,
+		&misc_p->ddr_pad_cfg);
+
+	ddr_pad_compensation(0);
+	spear13xx_ddr_level();
+	ddr_pad_compensation(1);
+}
+
+void soc_init(void)
+{
+	struct spear1310_misc_regs *const misc_p =
+		(struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+	/* Initialize PLLs */
+	sys_init();
+
+	/* Enable IPs (release reset) */
+	writel(SPEAR1310_PERIPH1_RST_ALL, &misc_p->perip1_sw_rst);
+	writel(SPEAR1310_PERIPH2_RST_ALL, &misc_p->perip2_sw_rst);
+	writel(SPEAR1310_RAS_RST_ALL, &misc_p->ras_sw_rst);
+}
diff --git a/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h b/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h
index 8d8278e..0d78b05 100644
--- a/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h
+++ b/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h
@@ -22,8 +22,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __SPEAR1310_REVC_MISC_H
-#define __SPEAR1310_REVC_MISC_H
+#ifndef __SPEAR1310_MISC_H
+#define __SPEAR1310_MISC_H
 
 struct spear1310_misc_regs {
 	u32 soc_cfg;				/* 0x000 */
@@ -238,27 +238,35 @@ struct spear1310_misc_regs {
 	u32 misc_cfg;				/* 0x1004 */
 };
 
-/* PHERIP1_CLOCK ENABLE */
-#define SPEAR1310_C3_CLKEN		0x20000000
-#define SPEAR1310_GPT1_CLKEN		0x00200000
-#define SPEAR1310_I2C_CLKEN		0x00040000
-#define SPEAR1310_SSP_CLKEN		0x00020000
-#define SPEAR1310_UART_CLKEN		0x00008000
-#define SPEAR1310_UDC_UPD_CLKEN		0x00000800
-#define SPEAR1310_UHC1_CLKEN		0x00000200
-#define SPEAR1310_GETH_CLKEN		0x00000100
-#define SPEAR1310_SD_CLKEN		0x00000040
-#define SPEAR1310_SMI_CLKEN		0x00000020
-#define SPEAR1310_FSMC_CLKEN		0x00000010
+/* sys_clk_ctrl definitions */
+#define SPEAR1310_SYS_MODE_MASK		0x00000007
+#define SPEAR1310_SYS_MODE_REQ_DOZE	0x00000001
+#define SPEAR1310_SYS_MODE_REQ_SLOW	0x00000002
+#define SPEAR1310_SYS_MODE_REQ_NORMAL	0x00000004
+#define SPEAR1310_PLL_TIMEOUT_ENB	0x00000008
+#define SPEAR1310_XTAL_TIMEOUT_ENB	0x00000010
+#define SPEAR1310_SYS_STATE_MASK	0x000F0000
+#define SPEAR1310_SYS_STATE_NORMAL	0x000F0000
 
-/* perip1_sw_rst */
-#define SPEAR1310_C3_SWRST		0x20000000
-#define SPEAR1310_UDC_UPD_SWRST		0x00000800
-#define SPEAR1310_UHC1_SWRST		0x00000200
+/* sys_clk_*timer definitions */
+#define SPEAR1310_PLL_TIM		0x000007f8
+#define SPEAR1310_OSCI_TIM		0x000007f8
+
+/* pll_freq definitions in MHz */
+#define SPEAR1310_FREQ_1000		0x7D000006
+#define SPEAR1310_FREQ_533		0x6F000105
+#define SPEAR1310_FREQ_400		0x64000106
+#define SPEAR1310_FREQ_332		0x53000203
+#define SPEAR1310_FREQ_125		0x7D000306
+
+/* pll_ctr definitions */
+#define SPEAR1310_PLLLOCK		0x00000001
+#define SPEAR1310_PLLENABLE		0x00000004
 
 /* perip_clk_cfg definitions */
-#define SPEAR1310_UART48M		0x00000000
+#define SPEAR1310_MPMCCLKPLL4		0x00000400
 #define SPEAR1310_UARTCLKMSK		0x00000030
+#define SPEAR1310_UART48M		0x00000000
 
 /* gmac_clk_cfg definitions */
 #define SPEAR1310_PHYIF_MSK		0x00000070
@@ -273,10 +281,14 @@ struct spear1310_misc_regs {
 
 /* usbphy_gen_cfg definitions */
 #define SPEAR1310_USB_PLL_LOCK		0x01000000
+#define SPEAR1310_UTMI_XFER_RST2	0x00010000
+#define SPEAR1310_UTMI_XFER_RST1	0x00008000
+#define SPEAR1310_UTMI_XFER_RST0	0x00004000
 #define SPEAR1310_USBUTMI_RST		0x00008000
 #define SPEAR1310_USBPHY_RST		0x00002000
 #define SPEAR1310_USBPHY_POR		0x00001000
-#define SPEAR1310_COMMON_PWDN		0x00000000
+#define SPEAR1310_AUTOPPD_ON_OVRCURR	0x00000020
+#define SPEAR1310_COMMON_PWDN		0x00000001
 
 /* perip_cfg definitions */
 #define SPEAR1310_MCIF_MSK		0x00000060
@@ -288,13 +300,59 @@ struct spear1310_misc_regs {
 #define SPEAR1310_NANDCS0_NORCS6	0x00000004
 #define SPEAR1310_NANDCS0_NORCS7	0x00000008
 
+/* mpmc_cfg definitions */
+#define SPEAR1310_AXI2_AWCOBUF		0x04000000
+#define SPEAR1310_AXI0_AWCOBUF		0x01000000
+#define SPEAR1310_AXI2_CMDTHRESH_MSK	0x00000F00
+#define SPEAR1310_AXI2_CMDTHRESH_1	0x00000100
+#define SPEAR1310_AXI0_CMDTHRESH_MSK	0x0000000F
+#define SPEAR1310_AXI0_CMDTHRESH_1	0x00000001
+
 /* synth registers definitions */
 #define SPEAR1310_SYNT_CLKENB		0x80000000
-#define SPEAR1310_SYNT_FIN_FULL		0x04000000
+#define SPEAR1310_SYNT_FINFULL		0x04000000
 #define SPEAR1310_SYNT_X_1		0x00010000
 #define SPEAR1310_SYNT_X_2		0x00020000
 #define SPEAR1310_SYNT_Y_2		0x00000002
 #define SPEAR1310_SYNT_Y_5		0x00000005
 #define SPEAR1310_SYNT_Y_21		0x00000015
 
+/* PHERIP1_CLOCK ENABLE */
+#define SPEAR1310_C3_CLKEN		0x20000000
+#define SPEAR1310_GPT1_CLKEN		0x00200000
+#define SPEAR1310_I2C_CLKEN		0x00040000
+#define SPEAR1310_SSP_CLKEN		0x00020000
+#define SPEAR1310_UART_CLKEN		0x00008000
+#define SPEAR1310_UDC_UPD_CLKEN		0x00000800
+#define SPEAR1310_UHC1_CLKEN		0x00000200
+#define SPEAR1310_GETH_CLKEN		0x00000100
+#define SPEAR1310_SD_CLKEN		0x00000040
+#define SPEAR1310_SMI_CLKEN		0x00000020
+#define SPEAR1310_FSMC_CLKEN		0x00000010
+#define SPEAR1310_DDRCORE_CLKEN		0x00000002
+#define SPEAR1310_DDRCTRL_CLKEN		0x00000001
+
+/* perip1_sw_rst */
+#define SPEAR1310_C3_SWRST		0x20000000
+#define SPEAR1310_UDC_UPD_SWRST		0x00000800
+#define SPEAR1310_UHC1_SWRST		0x00000200
+#define SPEAR1310_DDRCORE_RST		0x00000002
+#define SPEAR1310_DDRCTRL_RST		0x00000001
+#define SPEAR1310_PERIPH1_RST_ALL	0x00000000
+#define SPEAR1310_PERIPH2_RST_ALL	0x00000000
+#define SPEAR1310_RAS_RST_ALL		0x00000000
+
+
+/* ddr_pad_cfg definitions */
+#define SPEAR1310_PAD_VREF		0x00000200
+#define SPEAR1310_DATA_PROGB		0x00000100
+#define SPEAR1310_DATA_PROGA		0x00000080
+#define SPEAR1310_CLK_PROGB		0x00000040
+#define SPEAR1310_CLK_PROGA		0x00000020
+#define SPEAR1310_CTRL_PROGB		0x00000010
+#define SPEAR1310_CTRL_PROGA		0x00000008
+#define SPEAR1310_DDR3_PAD_SW_SEL	0x00000004
+#define SPEAR1310_DDR3_PAD_SEL		0x00000002
+#define SPEAR1310_DDR3_SW_SEL		0x00000001
+
 #endif
diff --git a/board/st/spear13xx/config.mk b/board/st/spear13xx/config.mk
index a8f67d4..49cc280 100644
--- a/board/st/spear13xx/config.mk
+++ b/board/st/spear13xx/config.mk
@@ -23,8 +23,5 @@
 
 ifndef CONFIG_SPL_BUILD
 ALL-y += $(obj)u-boot.img
-
-ifdef CONFIG_MACH_SPEAR1340EVB
 ALL-y += $(obj)spl/u-boot-spl.img
 endif
-endif
diff --git a/board/st/spear13xx/spl-spear1310evb.c b/board/st/spear13xx/spl-spear1310evb.c
new file mode 100644
index 0000000..fe11eb5
--- /dev/null
+++ b/board/st/spear13xx/spl-spear1310evb.c
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+
+void board_pre_ddrinit(void)
+{
+	/*
+	 * Several provisions are present on board for Power Management wrt DDR
+	 *
+	 * There are 2 controls with the board that it can manipulate
+	 *  - PLGPIO 145: Controls DDR_CKE
+	 *  - PLGPIO 146: Controls DDR_nRESET
+	 */
+
+	/*
+	 * The selected configuration is as follows
+	 *  - DDR_nRESET, DDR_CKE : Force 0 in GPIO output mode
+	 *    (Additionally, activate pull down on both signals)
+	 */
+	spear1310_configure_pin(145, PMX_GPIO);
+	spear1310_configure_pin(146, PMX_GPIO);
+	spear1310_plgpio_set(145, 0);
+	spear1310_plgpio_set(146, 0);
+
+	/* Activate PULL DOWN on both EN_DDR_CKE and EN_DDR_nRST */
+	spear1310_configure_pin(145, PMX_PULLDOWN);
+	spear1310_configure_pin(146, PMX_PULLDOWN);
+}
diff --git a/include/configs/spear1310-evb.h b/include/configs/spear1310-evb.h
index 6c21cf4..b36c644 100644
--- a/include/configs/spear1310-evb.h
+++ b/include/configs/spear1310-evb.h
@@ -81,6 +81,11 @@
 #define CONFIG_NAND_FSMC
 #define CONFIG_SYS_FSMC_NAND_8BIT
 
+/* SPL support */
+#define CONFIG_SPL
+#define CONFIG_DDR_MT41J256M8
+#define CONFIG_SPEAR_DDRFREQ533
+
 /* Environment Variable configs */
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 	/* Environment is in serial NOR flash */
diff --git a/spl/Makefile b/spl/Makefile
index 78cb0a6..289758e 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -47,6 +47,7 @@ LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o
 LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/libdisk.o
 LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/libi2c.o
 LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/libgpio.o
+LIBS-$(CONFIG_SPL_MISC_SUPPORT) += drivers/misc/c3.o
 LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/libmmc.o
 LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/libserial.o
 LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o
