| Message ID | 839f475cc75c97ffb3496a4caa93de2faabdbca2.1645629688.git.michal.simek@xilinx.com |
|---|---|
| State | Deferred |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | gpio: slg7xl45106: Add support for slg7xl45106 i2c gpo expander | expand |
Hello Michal, On 23.02.22 16:21, Michal Simek wrote: > From: T Karthik Reddy <t.karthik.reddy@xilinx.com> > > slg7xl45106 is i2c based 8-bit gpo expander, gpo pins are set and get by > writing and reading corresponding gpo bit value into its data register. > > Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > MAINTAINERS | 1 + > drivers/gpio/Kconfig | 8 +++ > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio_slg7xl45106.c | 115 ++++++++++++++++++++++++++++++++ > 4 files changed, 125 insertions(+) > create mode 100644 drivers/gpio/gpio_slg7xl45106.c Reviewed-by: Heiko Schocher <hs@denx.de> Nitpick only, fix typo in subject s/gpo/gpio bye, Heiko
On 2/28/22 06:27, Heiko Schocher wrote: > Hello Michal, > > On 23.02.22 16:21, Michal Simek wrote: >> From: T Karthik Reddy <t.karthik.reddy@xilinx.com> >> >> slg7xl45106 is i2c based 8-bit gpo expander, gpo pins are set and get by >> writing and reading corresponding gpo bit value into its data register. >> >> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> >> Signed-off-by: Michal Simek <michal.simek@xilinx.com> >> --- >> >> MAINTAINERS | 1 + >> drivers/gpio/Kconfig | 8 +++ >> drivers/gpio/Makefile | 1 + >> drivers/gpio/gpio_slg7xl45106.c | 115 ++++++++++++++++++++++++++++++++ >> 4 files changed, 125 insertions(+) >> create mode 100644 drivers/gpio/gpio_slg7xl45106.c > > Reviewed-by: Heiko Schocher <hs@denx.de> > > Nitpick only, fix typo in subject > s/gpo/gpio GPO is correct. This is output only device. There is no way to read anything back. Thanks, Michal
Hi Michal, On Wed, 23 Feb 2022 at 08:21, Michal Simek <michal.simek@xilinx.com> wrote: > > From: T Karthik Reddy <t.karthik.reddy@xilinx.com> > > slg7xl45106 is i2c based 8-bit gpo expander, gpo pins are set and get by > writing and reading corresponding gpo bit value into its data register. > > Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > MAINTAINERS | 1 + > drivers/gpio/Kconfig | 8 +++ > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio_slg7xl45106.c | 115 ++++++++++++++++++++++++++++++++ > 4 files changed, 125 insertions(+) > create mode 100644 drivers/gpio/gpio_slg7xl45106.c You might consider reducing the length of the 'slg7xl45106_i2c_gpo' prefix. Also did you know about dm_i2c_reg_clrset() ? Reviewed-by: Simon Glass <sjg@chromium.org> Regards, SImon
On 3/1/22 15:58, Simon Glass wrote: > Hi Michal, > > On Wed, 23 Feb 2022 at 08:21, Michal Simek <michal.simek@xilinx.com> wrote: >> >> From: T Karthik Reddy <t.karthik.reddy@xilinx.com> >> >> slg7xl45106 is i2c based 8-bit gpo expander, gpo pins are set and get by >> writing and reading corresponding gpo bit value into its data register. >> >> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> >> Signed-off-by: Michal Simek <michal.simek@xilinx.com> >> --- >> >> MAINTAINERS | 1 + >> drivers/gpio/Kconfig | 8 +++ >> drivers/gpio/Makefile | 1 + >> drivers/gpio/gpio_slg7xl45106.c | 115 ++++++++++++++++++++++++++++++++ >> 4 files changed, 125 insertions(+) >> create mode 100644 drivers/gpio/gpio_slg7xl45106.c > > You might consider reducing the length of the 'slg7xl45106_i2c_gpo' prefix. > > Also did you know about dm_i2c_reg_clrset() ? nope but logic there is a little bit different compare to what I need to do. It can be done but this I can't see this as a problem. > > Reviewed-by: Simon Glass <sjg@chromium.org> Thanks, Michal
st 23. 2. 2022 v 16:21 odesÃlatel Michal Simek <michal.simek@xilinx.com> napsal: > > From: T Karthik Reddy <t.karthik.reddy@xilinx.com> > > slg7xl45106 is i2c based 8-bit gpo expander, gpo pins are set and get by > writing and reading corresponding gpo bit value into its data register. > > Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > MAINTAINERS | 1 + > drivers/gpio/Kconfig | 8 +++ > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio_slg7xl45106.c | 115 ++++++++++++++++++++++++++++++++ > 4 files changed, 125 insertions(+) > create mode 100644 drivers/gpio/gpio_slg7xl45106.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index a75f429cb972..055d7ec2043c 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -638,6 +638,7 @@ F: arch/arm/mach-zynqmp/ > F: drivers/clk/clk_zynqmp.c > F: driver/firmware/firmware-zynqmp.c > F: drivers/fpga/zynqpl.c > +F: drivers/gpio/gpio_slg7xl45106.c > F: drivers/gpio/zynq_gpio.c > F: drivers/gpio/zynqmp_gpio_modepin.c > F: drivers/i2c/i2c-cdns.c > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 8d0e47c67d9e..a9b3bb854f09 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -544,4 +544,12 @@ config ZYNQMP_GPIO_MODEPIN > are accessed using xilinx firmware. In modepin register, [3:0] bits > set direction, [7:4] bits read IO, [11:8] bits set/clear IO. > > +config SLG7XL45106_I2C_GPO > + bool "slg7xl45106 i2c gpo expander" > + depends on DM_GPIO > + help > + Support for slg7xl45106 i2c gpo expander. It is an i2c based > + 8-bit gpo expander, all gpo lines are controlled by writing > + value into data register. > + > endif > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile > index 63e9be6034f2..dd288c497a70 100644 > --- a/drivers/gpio/Makefile > +++ b/drivers/gpio/Makefile > @@ -71,3 +71,4 @@ obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o > obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o > obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o > obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o > +obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o > diff --git a/drivers/gpio/gpio_slg7xl45106.c b/drivers/gpio/gpio_slg7xl45106.c > new file mode 100644 > index 000000000000..2cbf7488ad62 > --- /dev/null > +++ b/drivers/gpio/gpio_slg7xl45106.c > @@ -0,0 +1,115 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * slg7xl45106_i2c_gpo driver > + * > + * Copyright (C) 2021 Xilinx, Inc. > + */ > + > +#include <common.h> > +#include <errno.h> > +#include <asm/io.h> > +#include <asm/gpio.h> > +#include <dm.h> > +#include <i2c.h> > +#include <asm/arch/hardware.h> > + > +#define SLG7XL45106_REG 0xdb > + > +static int slg7xl45106_i2c_gpo_direction_input(struct udevice *dev, > + unsigned int offset) > +{ > + return 0; > +} > + > +static int slg7xl45106_i2c_gpo_xlate(struct udevice *dev, > + struct gpio_desc *desc, > + struct ofnode_phandle_args *args) > +{ > + desc->offset = (unsigned int)args->args[0]; > + > + return 0; > +} > + > +static int slg7xl45106_i2c_gpo_set_value(struct udevice *dev, > + unsigned int offset, int value) > +{ > + int ret; > + u8 val; > + > + ret = dm_i2c_read(dev, SLG7XL45106_REG, &val, 1); > + if (ret) > + return ret; > + > + if (value) > + val |= BIT(offset); > + else > + val &= ~BIT(offset); > + > + return dm_i2c_write(dev, SLG7XL45106_REG, &val, 1); > +} > + > +static int slg7xl45106_i2c_gpo_direction_output(struct udevice *dev, > + unsigned int offset, int value) > +{ > + return slg7xl45106_i2c_gpo_set_value(dev, offset, value); > +} > + > +static int slg7xl45106_i2c_gpo_get_value(struct udevice *dev, > + unsigned int offset) > +{ > + int ret; > + u8 val; > + > + ret = dm_i2c_read(dev, SLG7XL45106_REG, &val, 1); > + if (ret) > + return ret; > + > + return !!(val & BIT(offset)); > +} > + > +static int slg7xl45106_i2c_gpo_get_function(struct udevice *dev, > + unsigned int offset) > +{ > + return GPIOF_OUTPUT; > +} > + > +static const struct dm_gpio_ops slg7xl45106_i2c_gpo_ops = { > + .direction_input = slg7xl45106_i2c_gpo_direction_input, > + .direction_output = slg7xl45106_i2c_gpo_direction_output, > + .get_value = slg7xl45106_i2c_gpo_get_value, > + .set_value = slg7xl45106_i2c_gpo_set_value, > + .get_function = slg7xl45106_i2c_gpo_get_function, > + .xlate = slg7xl45106_i2c_gpo_xlate, > +}; > + > +static int slg7xl45106_i2c_gpo_probe(struct udevice *dev) > +{ > + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); > + const void *label_ptr; > + > + label_ptr = dev_read_prop(dev, "label", NULL); > + if (label_ptr) { > + uc_priv->bank_name = strdup(label_ptr); > + if (!uc_priv->bank_name) > + return -ENOMEM; > + } else { > + uc_priv->bank_name = dev->name; > + } > + > + uc_priv->gpio_count = 8; > + > + return 0; > +} > + > +static const struct udevice_id slg7xl45106_i2c_gpo_ids[] = { > + { .compatible = "dlg,slg7xl45106",}, > + { } > +}; > + > +U_BOOT_DRIVER(slg7xl45106_i2c_gpo) = { > + .name = "slg7xl45106_i2c_gpo", > + .id = UCLASS_GPIO, > + .ops = &slg7xl45106_i2c_gpo_ops, > + .of_match = slg7xl45106_i2c_gpo_ids, > + .probe = slg7xl45106_i2c_gpo_probe, > +}; > -- > 2.35.1 > Applied. M
diff --git a/MAINTAINERS b/MAINTAINERS index a75f429cb972..055d7ec2043c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -638,6 +638,7 @@ F: arch/arm/mach-zynqmp/ F: drivers/clk/clk_zynqmp.c F: driver/firmware/firmware-zynqmp.c F: drivers/fpga/zynqpl.c +F: drivers/gpio/gpio_slg7xl45106.c F: drivers/gpio/zynq_gpio.c F: drivers/gpio/zynqmp_gpio_modepin.c F: drivers/i2c/i2c-cdns.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8d0e47c67d9e..a9b3bb854f09 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -544,4 +544,12 @@ config ZYNQMP_GPIO_MODEPIN are accessed using xilinx firmware. In modepin register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits set/clear IO. +config SLG7XL45106_I2C_GPO + bool "slg7xl45106 i2c gpo expander" + depends on DM_GPIO + help + Support for slg7xl45106 i2c gpo expander. It is an i2c based + 8-bit gpo expander, all gpo lines are controlled by writing + value into data register. + endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 63e9be6034f2..dd288c497a70 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -71,3 +71,4 @@ obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o +obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o diff --git a/drivers/gpio/gpio_slg7xl45106.c b/drivers/gpio/gpio_slg7xl45106.c new file mode 100644 index 000000000000..2cbf7488ad62 --- /dev/null +++ b/drivers/gpio/gpio_slg7xl45106.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * slg7xl45106_i2c_gpo driver + * + * Copyright (C) 2021 Xilinx, Inc. + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <dm.h> +#include <i2c.h> +#include <asm/arch/hardware.h> + +#define SLG7XL45106_REG 0xdb + +static int slg7xl45106_i2c_gpo_direction_input(struct udevice *dev, + unsigned int offset) +{ + return 0; +} + +static int slg7xl45106_i2c_gpo_xlate(struct udevice *dev, + struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + desc->offset = (unsigned int)args->args[0]; + + return 0; +} + +static int slg7xl45106_i2c_gpo_set_value(struct udevice *dev, + unsigned int offset, int value) +{ + int ret; + u8 val; + + ret = dm_i2c_read(dev, SLG7XL45106_REG, &val, 1); + if (ret) + return ret; + + if (value) + val |= BIT(offset); + else + val &= ~BIT(offset); + + return dm_i2c_write(dev, SLG7XL45106_REG, &val, 1); +} + +static int slg7xl45106_i2c_gpo_direction_output(struct udevice *dev, + unsigned int offset, int value) +{ + return slg7xl45106_i2c_gpo_set_value(dev, offset, value); +} + +static int slg7xl45106_i2c_gpo_get_value(struct udevice *dev, + unsigned int offset) +{ + int ret; + u8 val; + + ret = dm_i2c_read(dev, SLG7XL45106_REG, &val, 1); + if (ret) + return ret; + + return !!(val & BIT(offset)); +} + +static int slg7xl45106_i2c_gpo_get_function(struct udevice *dev, + unsigned int offset) +{ + return GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops slg7xl45106_i2c_gpo_ops = { + .direction_input = slg7xl45106_i2c_gpo_direction_input, + .direction_output = slg7xl45106_i2c_gpo_direction_output, + .get_value = slg7xl45106_i2c_gpo_get_value, + .set_value = slg7xl45106_i2c_gpo_set_value, + .get_function = slg7xl45106_i2c_gpo_get_function, + .xlate = slg7xl45106_i2c_gpo_xlate, +}; + +static int slg7xl45106_i2c_gpo_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + const void *label_ptr; + + label_ptr = dev_read_prop(dev, "label", NULL); + if (label_ptr) { + uc_priv->bank_name = strdup(label_ptr); + if (!uc_priv->bank_name) + return -ENOMEM; + } else { + uc_priv->bank_name = dev->name; + } + + uc_priv->gpio_count = 8; + + return 0; +} + +static const struct udevice_id slg7xl45106_i2c_gpo_ids[] = { + { .compatible = "dlg,slg7xl45106",}, + { } +}; + +U_BOOT_DRIVER(slg7xl45106_i2c_gpo) = { + .name = "slg7xl45106_i2c_gpo", + .id = UCLASS_GPIO, + .ops = &slg7xl45106_i2c_gpo_ops, + .of_match = slg7xl45106_i2c_gpo_ids, + .probe = slg7xl45106_i2c_gpo_probe, +};